From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1B5C71 for ; Thu, 20 May 2021 01:59:17 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 3D01B611BF for ; Thu, 20 May 2021 01:59:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621475957; bh=JdmBtI/nybX20LTYzwdeu3sRM7FFnENPxyFNjn3PhTc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=aQy9ccJsdFmRayoAiTGj43uqjruUasRMW3XaC7Y51U6ChraF+gd4VnB5Mm47kDzoF YtOxGgjcaqZept35IaUQW0QVaeAhwRn2ILFnGyv9rjSwh+marLBoRCyIbJ/p6xFnft V2MQ4C4f2aWrFpBp6vD41RmLBy5yWatN4r39rw8hffgO+MRPVrijETmZN5SYhNHtC6 ZJtWFpbhBZRS9NwBEwEiN3/i/Yw67Xq4F7h1bfNd9n9SMfgpmkqUqZG/X5yLoUNN5J KR0y8HJp7SkFTsys/rn8aSejDiLFMkfizOeXOFWduU2BGIsxKMnNxfTzGVg9KmA8yw 9magqsOUmrp8A== Received: by mail-lf1-f49.google.com with SMTP id v8so17014097lft.8 for ; Wed, 19 May 2021 18:59:17 -0700 (PDT) X-Gm-Message-State: AOAM533GxJjQvnLU+REa0V+NyPHN+y+b1jfusuX7WKhx6qxCzqmTn6Jl PFuI+wZxWxYvXpNsV+Mle8w2m5F4W1zvrkJ5HGA= X-Google-Smtp-Source: ABdhPJx4Yk2C9GqxDVxay2oozMIz1ibiukYQwG5GLFDi0mjK8VBRld1CDnMtfMIba/K4AMweT0lkvN1tYYTAfnwELo4= X-Received: by 2002:ac2:5493:: with SMTP id t19mr1678843lfk.346.1621475955570; Wed, 19 May 2021 18:59:15 -0700 (PDT) X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519060617.GA28397@lst.de> <20210519065431.GB3076809@x1> In-Reply-To: From: Guo Ren Date: Thu, 20 May 2021 09:59:04 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Anup Patel Cc: Drew Fustini , Christoph Hellwig , Anup Patel , Palmer Dabbelt , wefu@redhat.com, =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley Content-Type: text/plain; charset="UTF-8" On Thu, May 20, 2021 at 9:47 AM Guo Ren wrote: > > On Wed, May 19, 2021 at 3:15 PM Anup Patel wrote: > > > > On Wed, May 19, 2021 at 12:24 PM Drew Fustini wrote: > > > > > > On Wed, May 19, 2021 at 08:06:17AM +0200, Christoph Hellwig wrote: > > > > On Wed, May 19, 2021 at 02:05:00PM +0800, Guo Ren wrote: > > > > > Since the existing RISC-V ISA cannot solve this problem, it is better > > > > > to provide some configuration for the SOC vendor to customize. > > > > > > > > We've been talking about this problem for close to five years. So no, > > > > if you don't manage to get the feature into the ISA it can't be > > > > supported. > > > > > > Isn't it a good goal for Linux to support the capabilities present in > > > the SoC that a currently being fab'd? > > > > > > I believe the CMO group only started last year [1] so the RV64GC SoCs > > > that are going into mass production this year would not have had the > > > opporuntiy of utilizing any RISC-V ISA extension for handling cache > > > management. > > > > The current Linux RISC-V policy is to only accept patches for frozen or > > ratified ISA specs. > > (Refer, Documentation/riscv/patch-acceptance.rst) > > > > This means even if emulate CMO instructions in OpenSBI, the Linux I think it's CBO now. https://github.com/riscv/riscv-CMOs/blob/master/discussion-files/RISC_V_range_CMOs_bad_v1.00.pdf > > patches won't be taken by Palmer because CMO specification is > > still in draft stage. > How do you think about > sbi_ecall(SBI_EXT_DMA, SBI_DMA_SYNC, start, size, dir, 0, 0, 0); > ? thx CBO insn trap is okay for me ;-) > > > > Also, we all know how much time it takes for RISCV international > > to freeze some spec. Judging by that we are looking at another > > 3-4 years at minimum. > > > > Regards, > > Anup > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26AF8C433B4 for ; Thu, 20 May 2021 01:59:46 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 768B0611AE for ; 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Wed, 19 May 2021 18:59:15 -0700 (PDT) MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519060617.GA28397@lst.de> <20210519065431.GB3076809@x1> In-Reply-To: From: Guo Ren Date: Thu, 20 May 2021 09:59:04 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Anup Patel Cc: Drew Fustini , Christoph Hellwig , Anup Patel , Palmer Dabbelt , wefu@redhat.com, =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_185918_014208_2720C469 X-CRM114-Status: GOOD ( 29.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 20, 2021 at 9:47 AM Guo Ren wrote: > > On Wed, May 19, 2021 at 3:15 PM Anup Patel wrote: > > > > On Wed, May 19, 2021 at 12:24 PM Drew Fustini wrote: > > > > > > On Wed, May 19, 2021 at 08:06:17AM +0200, Christoph Hellwig wrote: > > > > On Wed, May 19, 2021 at 02:05:00PM +0800, Guo Ren wrote: > > > > > Since the existing RISC-V ISA cannot solve this problem, it is better > > > > > to provide some configuration for the SOC vendor to customize. > > > > > > > > We've been talking about this problem for close to five years. So no, > > > > if you don't manage to get the feature into the ISA it can't be > > > > supported. > > > > > > Isn't it a good goal for Linux to support the capabilities present in > > > the SoC that a currently being fab'd? > > > > > > I believe the CMO group only started last year [1] so the RV64GC SoCs > > > that are going into mass production this year would not have had the > > > opporuntiy of utilizing any RISC-V ISA extension for handling cache > > > management. > > > > The current Linux RISC-V policy is to only accept patches for frozen or > > ratified ISA specs. > > (Refer, Documentation/riscv/patch-acceptance.rst) > > > > This means even if emulate CMO instructions in OpenSBI, the Linux I think it's CBO now. https://github.com/riscv/riscv-CMOs/blob/master/discussion-files/RISC_V_range_CMOs_bad_v1.00.pdf > > patches won't be taken by Palmer because CMO specification is > > still in draft stage. > How do you think about > sbi_ecall(SBI_EXT_DMA, SBI_DMA_SYNC, start, size, dir, 0, 0, 0); > ? thx CBO insn trap is okay for me ;-) > > > > Also, we all know how much time it takes for RISCV international > > to freeze some spec. Judging by that we are looking at another > > 3-4 years at minimum. > > > > Regards, > > Anup > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv