From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFD79C5B576 for ; Sun, 30 Jun 2019 04:32:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B9AE02089C for ; Sun, 30 Jun 2019 04:32:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1561869159; bh=cQSFOfkpKMob0CUu8153N6DUVyC3npdxm62i1j4VpIw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=Khkz6zTZsbQQdRCN3u9ArYl4cG64apj2wIV7kG3lagjmqGB9VgJu5XvtjtSc7Y9RM 6pk28ASib2g4GA4XehWDQ9+sWleQZ1eGOvs6LtNyZASGN7cNr5MZwt/Wr1cFgi6ES+ xj8uBtqapZFvJDx7QalU8TpBQ3eSDKljFe3SUS48= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726467AbfF3EaB (ORCPT ); Sun, 30 Jun 2019 00:30:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:34542 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725771AbfF3EaB (ORCPT ); Sun, 30 Jun 2019 00:30:01 -0400 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6E81F2089C for ; Sun, 30 Jun 2019 04:29:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1561868999; bh=cQSFOfkpKMob0CUu8153N6DUVyC3npdxm62i1j4VpIw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=j72oOEAif2V94f0mwKfr5J/PRx+YFli4yICxddcq/LIiS7JQ+YKk1YGF4PSgQDKL7 IMJd+IOSbwJSo6k5b1N04qP590P8btcmtnruiRG/EpAmzvilpIrTFErZtfqeXBnnsi 04dlqRLB1LypljThQz/jstMx1/Gu9frEnC0Vy7yo= Received: by mail-wm1-f47.google.com with SMTP id n9so727523wmi.0 for ; Sat, 29 Jun 2019 21:29:59 -0700 (PDT) X-Gm-Message-State: APjAAAU/Qs/LYBXjGZdXLOqVa/fkwm+vsg9nqnOdr3UIh3ajMZkQIcH1 kgp3qsUv0KppIkqTIQn0e0sSp/43gkoFZtdIhC4= X-Google-Smtp-Source: APXvYqykrDoGZznjGRXJXJkVCBwA9280hX7gYGYy3Dbo1kbGt1iT4Zj+H8TCZ/zglBC8rdfd2ydmBM/xQE7cDlA9Xmo= X-Received: by 2002:a1c:6545:: with SMTP id z66mr12063849wmb.77.1561868998022; Sat, 29 Jun 2019 21:29:58 -0700 (PDT) MIME-Version: 1.0 References: <20190321163623.20219-1-julien.grall@arm.com> <20190321163623.20219-12-julien.grall@arm.com> <0dfe120b-066a-2ac8-13bc-3f5a29e2caa3@arm.com> <20190621141606.GF18954@arrakis.emea.arm.com> <20190624153820.GH29120@arrakis.emea.arm.com> In-Reply-To: <20190624153820.GH29120@arrakis.emea.arm.com> From: Guo Ren Date: Sun, 30 Jun 2019 12:29:46 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file To: Catalin Marinas Cc: Julien Grall , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, aou@eecs.berkeley.edu, gary@garyguo.net, Atish Patra , hch@infradead.org, paul.walmsley@sifive.com, rppt@linux.ibm.com, linux-riscv@lists.infradead.org, Anup Patel , Palmer Dabbelt , suzuki.poulose@arm.com, Marc Zyngier , julien.thierry@arm.com, Will Deacon , christoffer.dall@arm.com, james.morse@arm.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marinas, Thx for the reply On Mon, Jun 24, 2019 at 11:38 PM Catalin Marinas wrote: > > On Mon, Jun 24, 2019 at 12:35:35AM +0800, Guo Ren wrote: > > On Fri, Jun 21, 2019 at 10:16 PM Catalin Marinas > > wrote: > > > BTW, if you find the algorithm fairly straightforward ;), see this > > > bug-fix which took a formal model to identify: a8ffaaa060b8 ("arm64: > > > asid: Do not replace active_asids if already 0"). > [...] > > Btw, Is this detected by arm's aisd allocator TLA+ model ? Or a real > > bug report ? > > This specific bug was found by the TLA+ model checker (at the time we > were actually tracking down another bug with multi-threaded CPU sharing > the TLB, bug also confirmed by the formal model). Could you tell me the ref-link about "another bug with multi-threaded CPU sharing the TLB" ? In my concept, the multi-core asid mechanism is also applicable to multi-thread shared TLB, but it will generate redundant tlbflush. From the software design logic, multi-threaded is treated as multi-cores without error, but performance is not optimized. So in my RFC PATCH: [1], I try to reduce multi-threads' tlbflush in one CPU core with the fixed cpu ID bitmap hypothesis. 1: https://lore.kernel.org/linux-csky/CAJF2gTQ0xQtQY1t-g9FgWaxfDXppMkFooCQzTFy7+ouwUfyA6w@mail.gmail.com/T/#m2ed464d2dfb45ac6f5547fb3936adf2da456cb65 -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19323C5B576 for ; Sun, 30 Jun 2019 04:30:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1BEC2089C for ; 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Sun, 30 Jun 2019 04:29:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1561868999; bh=cQSFOfkpKMob0CUu8153N6DUVyC3npdxm62i1j4VpIw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=j72oOEAif2V94f0mwKfr5J/PRx+YFli4yICxddcq/LIiS7JQ+YKk1YGF4PSgQDKL7 IMJd+IOSbwJSo6k5b1N04qP590P8btcmtnruiRG/EpAmzvilpIrTFErZtfqeXBnnsi 04dlqRLB1LypljThQz/jstMx1/Gu9frEnC0Vy7yo= Received: by mail-wm1-f41.google.com with SMTP id a15so12623950wmj.5; Sat, 29 Jun 2019 21:29:59 -0700 (PDT) X-Gm-Message-State: APjAAAX41nFIrLqXKv1bHkB22Yu3mLNc0+JwBGW7ryD+I2JPLc7MCNHu PIF3B7JLSlE/e7va5PctQ/+95qTNNmLtoAoLE3k= X-Google-Smtp-Source: APXvYqykrDoGZznjGRXJXJkVCBwA9280hX7gYGYy3Dbo1kbGt1iT4Zj+H8TCZ/zglBC8rdfd2ydmBM/xQE7cDlA9Xmo= X-Received: by 2002:a1c:6545:: with SMTP id z66mr12063849wmb.77.1561868998022; Sat, 29 Jun 2019 21:29:58 -0700 (PDT) MIME-Version: 1.0 References: <20190321163623.20219-1-julien.grall@arm.com> <20190321163623.20219-12-julien.grall@arm.com> <0dfe120b-066a-2ac8-13bc-3f5a29e2caa3@arm.com> <20190621141606.GF18954@arrakis.emea.arm.com> <20190624153820.GH29120@arrakis.emea.arm.com> In-Reply-To: <20190624153820.GH29120@arrakis.emea.arm.com> From: Guo Ren Date: Sun, 30 Jun 2019 12:29:46 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file To: Catalin Marinas X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190629_213002_037781_0C39C691 X-CRM114-Status: GOOD ( 12.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, aou@eecs.berkeley.edu, james.morse@arm.com, suzuki.poulose@arm.com, Marc Zyngier , Anup Patel , Will Deacon , linux-kernel@vger.kernel.org, rppt@linux.ibm.com, hch@infradead.org, Atish Patra , Julien Grall , Palmer Dabbelt , gary@garyguo.net, paul.walmsley@sifive.com, christoffer.dall@arm.com, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Hi Marinas, Thx for the reply On Mon, Jun 24, 2019 at 11:38 PM Catalin Marinas wrote: > > On Mon, Jun 24, 2019 at 12:35:35AM +0800, Guo Ren wrote: > > On Fri, Jun 21, 2019 at 10:16 PM Catalin Marinas > > wrote: > > > BTW, if you find the algorithm fairly straightforward ;), see this > > > bug-fix which took a formal model to identify: a8ffaaa060b8 ("arm64: > > > asid: Do not replace active_asids if already 0"). > [...] > > Btw, Is this detected by arm's aisd allocator TLA+ model ? Or a real > > bug report ? > > This specific bug was found by the TLA+ model checker (at the time we > were actually tracking down another bug with multi-threaded CPU sharing > the TLB, bug also confirmed by the formal model). Could you tell me the ref-link about "another bug with multi-threaded CPU sharing the TLB" ? In my concept, the multi-core asid mechanism is also applicable to multi-thread shared TLB, but it will generate redundant tlbflush. From the software design logic, multi-threaded is treated as multi-cores without error, but performance is not optimized. So in my RFC PATCH: [1], I try to reduce multi-threads' tlbflush in one CPU core with the fixed cpu ID bitmap hypothesis. 1: https://lore.kernel.org/linux-csky/CAJF2gTQ0xQtQY1t-g9FgWaxfDXppMkFooCQzTFy7+ouwUfyA6w@mail.gmail.com/T/#m2ed464d2dfb45ac6f5547fb3936adf2da456cb65 -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B4F4C5B576 for ; Sun, 30 Jun 2019 04:30:06 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id B732A2089C for ; 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h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=j72oOEAif2V94f0mwKfr5J/PRx+YFli4yICxddcq/LIiS7JQ+YKk1YGF4PSgQDKL7 IMJd+IOSbwJSo6k5b1N04qP590P8btcmtnruiRG/EpAmzvilpIrTFErZtfqeXBnnsi 04dlqRLB1LypljThQz/jstMx1/Gu9frEnC0Vy7yo= Received: by mail-wm1-f50.google.com with SMTP id f17so12497748wme.2 for ; Sat, 29 Jun 2019 21:29:59 -0700 (PDT) X-Gm-Message-State: APjAAAVvtuxjeRGc1I3X+f7Rog5YIyp+udfikmV/3o7vEU2zz7vtbO7e m02Q3B27FJ3O0jwP5TsEhUKZv0fVi7bKt8ctR5M= X-Google-Smtp-Source: APXvYqykrDoGZznjGRXJXJkVCBwA9280hX7gYGYy3Dbo1kbGt1iT4Zj+H8TCZ/zglBC8rdfd2ydmBM/xQE7cDlA9Xmo= X-Received: by 2002:a1c:6545:: with SMTP id z66mr12063849wmb.77.1561868998022; Sat, 29 Jun 2019 21:29:58 -0700 (PDT) MIME-Version: 1.0 References: <20190321163623.20219-1-julien.grall@arm.com> <20190321163623.20219-12-julien.grall@arm.com> <0dfe120b-066a-2ac8-13bc-3f5a29e2caa3@arm.com> <20190621141606.GF18954@arrakis.emea.arm.com> <20190624153820.GH29120@arrakis.emea.arm.com> In-Reply-To: <20190624153820.GH29120@arrakis.emea.arm.com> From: Guo Ren Date: Sun, 30 Jun 2019 12:29:46 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file To: Catalin Marinas Cc: aou@eecs.berkeley.edu, Marc Zyngier , Anup Patel , Will Deacon , linux-kernel@vger.kernel.org, rppt@linux.ibm.com, hch@infradead.org, Atish Patra , Julien Grall , Palmer Dabbelt , gary@garyguo.net, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marinas, Thx for the reply On Mon, Jun 24, 2019 at 11:38 PM Catalin Marinas wrote: > > On Mon, Jun 24, 2019 at 12:35:35AM +0800, Guo Ren wrote: > > On Fri, Jun 21, 2019 at 10:16 PM Catalin Marinas > > wrote: > > > BTW, if you find the algorithm fairly straightforward ;), see this > > > bug-fix which took a formal model to identify: a8ffaaa060b8 ("arm64: > > > asid: Do not replace active_asids if already 0"). > [...] > > Btw, Is this detected by arm's aisd allocator TLA+ model ? Or a real > > bug report ? > > This specific bug was found by the TLA+ model checker (at the time we > were actually tracking down another bug with multi-threaded CPU sharing > the TLB, bug also confirmed by the formal model). Could you tell me the ref-link about "another bug with multi-threaded CPU sharing the TLB" ? In my concept, the multi-core asid mechanism is also applicable to multi-thread shared TLB, but it will generate redundant tlbflush. From the software design logic, multi-threaded is treated as multi-cores without error, but performance is not optimized. So in my RFC PATCH: [1], I try to reduce multi-threads' tlbflush in one CPU core with the fixed cpu ID bitmap hypothesis. 1: https://lore.kernel.org/linux-csky/CAJF2gTQ0xQtQY1t-g9FgWaxfDXppMkFooCQzTFy7+ouwUfyA6w@mail.gmail.com/T/#m2ed464d2dfb45ac6f5547fb3936adf2da456cb65 -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D6EEC5B576 for ; Sun, 30 Jun 2019 04:30:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45E402089C for ; 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Sun, 30 Jun 2019 04:29:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1561868999; bh=cQSFOfkpKMob0CUu8153N6DUVyC3npdxm62i1j4VpIw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=j72oOEAif2V94f0mwKfr5J/PRx+YFli4yICxddcq/LIiS7JQ+YKk1YGF4PSgQDKL7 IMJd+IOSbwJSo6k5b1N04qP590P8btcmtnruiRG/EpAmzvilpIrTFErZtfqeXBnnsi 04dlqRLB1LypljThQz/jstMx1/Gu9frEnC0Vy7yo= Received: by mail-wm1-f41.google.com with SMTP id a15so12623950wmj.5; Sat, 29 Jun 2019 21:29:59 -0700 (PDT) X-Gm-Message-State: APjAAAX41nFIrLqXKv1bHkB22Yu3mLNc0+JwBGW7ryD+I2JPLc7MCNHu PIF3B7JLSlE/e7va5PctQ/+95qTNNmLtoAoLE3k= X-Google-Smtp-Source: APXvYqykrDoGZznjGRXJXJkVCBwA9280hX7gYGYy3Dbo1kbGt1iT4Zj+H8TCZ/zglBC8rdfd2ydmBM/xQE7cDlA9Xmo= X-Received: by 2002:a1c:6545:: with SMTP id z66mr12063849wmb.77.1561868998022; Sat, 29 Jun 2019 21:29:58 -0700 (PDT) MIME-Version: 1.0 References: <20190321163623.20219-1-julien.grall@arm.com> <20190321163623.20219-12-julien.grall@arm.com> <0dfe120b-066a-2ac8-13bc-3f5a29e2caa3@arm.com> <20190621141606.GF18954@arrakis.emea.arm.com> <20190624153820.GH29120@arrakis.emea.arm.com> In-Reply-To: <20190624153820.GH29120@arrakis.emea.arm.com> From: Guo Ren Date: Sun, 30 Jun 2019 12:29:46 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file To: Catalin Marinas X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190629_213002_037781_0C39C691 X-CRM114-Status: GOOD ( 12.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, aou@eecs.berkeley.edu, james.morse@arm.com, suzuki.poulose@arm.com, Marc Zyngier , Anup Patel , Will Deacon , linux-kernel@vger.kernel.org, rppt@linux.ibm.com, hch@infradead.org, Atish Patra , Julien Grall , Palmer Dabbelt , gary@garyguo.net, paul.walmsley@sifive.com, christoffer.dall@arm.com, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marinas, Thx for the reply On Mon, Jun 24, 2019 at 11:38 PM Catalin Marinas wrote: > > On Mon, Jun 24, 2019 at 12:35:35AM +0800, Guo Ren wrote: > > On Fri, Jun 21, 2019 at 10:16 PM Catalin Marinas > > wrote: > > > BTW, if you find the algorithm fairly straightforward ;), see this > > > bug-fix which took a formal model to identify: a8ffaaa060b8 ("arm64: > > > asid: Do not replace active_asids if already 0"). > [...] > > Btw, Is this detected by arm's aisd allocator TLA+ model ? Or a real > > bug report ? > > This specific bug was found by the TLA+ model checker (at the time we > were actually tracking down another bug with multi-threaded CPU sharing > the TLB, bug also confirmed by the formal model). Could you tell me the ref-link about "another bug with multi-threaded CPU sharing the TLB" ? In my concept, the multi-core asid mechanism is also applicable to multi-thread shared TLB, but it will generate redundant tlbflush. From the software design logic, multi-threaded is treated as multi-cores without error, but performance is not optimized. So in my RFC PATCH: [1], I try to reduce multi-threads' tlbflush in one CPU core with the fixed cpu ID bitmap hypothesis. 1: https://lore.kernel.org/linux-csky/CAJF2gTQ0xQtQY1t-g9FgWaxfDXppMkFooCQzTFy7+ouwUfyA6w@mail.gmail.com/T/#m2ed464d2dfb45ac6f5547fb3936adf2da456cb65 -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel