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Mon, 19 Sep 2022 23:36:46 -0700 (PDT) X-Gm-Message-State: ACrzQf2GpvFfkiylgh2wem/2YJe/N3mzGzsSCZHM63RJbJsdMXwNWPUL XLSIW6SRCOTKEhDXYWs97xBq17Wb6V5LmWvrD7o= X-Google-Smtp-Source: AMsMyM6uHFgQjuLTZDoq4Wi16bBED+ipq/0qPmivsB6oIlMREURn4RpqQ/Co7zUtuew7caXA1KRyrH6dB1OH9wPOjsU= X-Received: by 2002:a05:6870:a78e:b0:12b:542b:e5b2 with SMTP id x14-20020a056870a78e00b0012b542be5b2mr1178610oao.112.1663655805409; Mon, 19 Sep 2022 23:36:45 -0700 (PDT) MIME-Version: 1.0 References: <20220918155246.1203293-1-guoren@kernel.org> <20220918155246.1203293-8-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Tue, 20 Sep 2022 14:36:33 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V5 07/11] riscv: convert to generic entry To: Peter Zijlstra Cc: arnd@arndb.de, palmer@rivosinc.com, tglx@linutronix.de, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, palmer@dabbelt.com, paul.walmsley@sifive.com, mark.rutland@arm.com, zouyipeng@huawei.com, bigeasy@linutronix.de, David.Laight@aculab.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220919_233648_838286_2FB2EA8E X-CRM114-Status: GOOD ( 17.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 19, 2022 at 9:34 PM Peter Zijlstra wrote: > > On Sun, Sep 18, 2022 at 11:52:42AM -0400, guoren@kernel.org wrote: > > > @@ -123,18 +126,22 @@ int handle_misaligned_store(struct pt_regs *regs); > > > > asmlinkage void __trap_section do_trap_load_misaligned(struct pt_regs *regs) > > { > > + irqentry_state_t state = irqentry_enter(regs); > > if (!handle_misaligned_load(regs)) > > return; > > do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, > > "Oops - load address misaligned"); > > + irqentry_exit(regs, state); > > } > > > > asmlinkage void __trap_section do_trap_store_misaligned(struct pt_regs *regs) > > { > > + irqentry_state_t state = irqentry_enter(regs); > > if (!handle_misaligned_store(regs)) > > return; > > do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, > > "Oops - store (or AMO) address misaligned"); > > + irqentry_exit(regs, state); > > } > > #endif > > DO_ERROR_INFO(do_trap_store_fault, > > @@ -158,6 +165,8 @@ static inline unsigned long get_break_insn_length(unsigned long pc) > > > > asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) > > { > > + irqentry_state_t state = irqentry_enter(regs); > > + > > #ifdef CONFIG_KPROBES > > if (kprobe_single_step_handler(regs)) > > return; > > FWIW; on x86 I've classified many of the 'from-kernel' traps as > NMI-like, since those traps can happen from any context, including with > IRQs disabled. The do_trap_break is for ebreak instruction, not NMI. RISC-V NMI has separate CSR. ref: This proposal adds support for resumable non-maskable interrupts (RNMIs) to RISC-V. The extension adds four new CSRs (`mnepc`, `mncause`, `mnstatus`, and `mnscratch`) to hold the interrupted state, and a new instruction to resume from the RNMI handler. > > The basic shape of the trap handlers looks a little like: > > if (user_mode(regs)) { If nmi comes from user_mode, why we using irqenrty_enter/exit_from/to_user_mode instead of irqentry_nmi_enter/exit? > irqenrty_enter_from_user_mode(regs); > do_user_trap(); > irqentry_exit_to_user_mode(regs); > } else { > irqentry_state_t state = irqentry_nmi_enter(regs); > do_kernel_trap(); > irqentry_nmi_exit(regs, state); > } > > Not saying you have to match Risc-V in this patch-set, just something to > consider. I think the shape of the riscv NMI handler looks a little like this: asmlinkage __visible __trap_section void do_trap_nmi(struct pt_regs *regs) { irqentry_state_t state = irqentry_nmi_enter(regs); do_nmi_trap(); irqentry_nmi_exit(regs, state); } -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8119AECAAD8 for ; Tue, 20 Sep 2022 06:38:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231176AbiITGiW (ORCPT ); Tue, 20 Sep 2022 02:38:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229978AbiITGhu (ORCPT ); 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Mon, 19 Sep 2022 23:36:46 -0700 (PDT) X-Gm-Message-State: ACrzQf2nNfH1HpJgQE5HhSBknADMgwP7GCEP7vx4seBqcK8Mape9Are5 bJyYOvFWASfrkn3Tyo5OF6v1VMVwrtMCEV4VRYM= X-Google-Smtp-Source: AMsMyM6uHFgQjuLTZDoq4Wi16bBED+ipq/0qPmivsB6oIlMREURn4RpqQ/Co7zUtuew7caXA1KRyrH6dB1OH9wPOjsU= X-Received: by 2002:a05:6870:a78e:b0:12b:542b:e5b2 with SMTP id x14-20020a056870a78e00b0012b542be5b2mr1178610oao.112.1663655805409; Mon, 19 Sep 2022 23:36:45 -0700 (PDT) MIME-Version: 1.0 References: <20220918155246.1203293-1-guoren@kernel.org> <20220918155246.1203293-8-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Tue, 20 Sep 2022 14:36:33 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V5 07/11] riscv: convert to generic entry To: Peter Zijlstra Cc: arnd@arndb.de, palmer@rivosinc.com, tglx@linutronix.de, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, palmer@dabbelt.com, paul.walmsley@sifive.com, mark.rutland@arm.com, zouyipeng@huawei.com, bigeasy@linutronix.de, David.Laight@aculab.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 19, 2022 at 9:34 PM Peter Zijlstra wrote: > > On Sun, Sep 18, 2022 at 11:52:42AM -0400, guoren@kernel.org wrote: > > > @@ -123,18 +126,22 @@ int handle_misaligned_store(struct pt_regs *regs); > > > > asmlinkage void __trap_section do_trap_load_misaligned(struct pt_regs *regs) > > { > > + irqentry_state_t state = irqentry_enter(regs); > > if (!handle_misaligned_load(regs)) > > return; > > do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, > > "Oops - load address misaligned"); > > + irqentry_exit(regs, state); > > } > > > > asmlinkage void __trap_section do_trap_store_misaligned(struct pt_regs *regs) > > { > > + irqentry_state_t state = irqentry_enter(regs); > > if (!handle_misaligned_store(regs)) > > return; > > do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, > > "Oops - store (or AMO) address misaligned"); > > + irqentry_exit(regs, state); > > } > > #endif > > DO_ERROR_INFO(do_trap_store_fault, > > @@ -158,6 +165,8 @@ static inline unsigned long get_break_insn_length(unsigned long pc) > > > > asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) > > { > > + irqentry_state_t state = irqentry_enter(regs); > > + > > #ifdef CONFIG_KPROBES > > if (kprobe_single_step_handler(regs)) > > return; > > FWIW; on x86 I've classified many of the 'from-kernel' traps as > NMI-like, since those traps can happen from any context, including with > IRQs disabled. The do_trap_break is for ebreak instruction, not NMI. RISC-V NMI has separate CSR. ref: This proposal adds support for resumable non-maskable interrupts (RNMIs) to RISC-V. The extension adds four new CSRs (`mnepc`, `mncause`, `mnstatus`, and `mnscratch`) to hold the interrupted state, and a new instruction to resume from the RNMI handler. > > The basic shape of the trap handlers looks a little like: > > if (user_mode(regs)) { If nmi comes from user_mode, why we using irqenrty_enter/exit_from/to_user_mode instead of irqentry_nmi_enter/exit? > irqenrty_enter_from_user_mode(regs); > do_user_trap(); > irqentry_exit_to_user_mode(regs); > } else { > irqentry_state_t state = irqentry_nmi_enter(regs); > do_kernel_trap(); > irqentry_nmi_exit(regs, state); > } > > Not saying you have to match Risc-V in this patch-set, just something to > consider. I think the shape of the riscv NMI handler looks a little like this: asmlinkage __visible __trap_section void do_trap_nmi(struct pt_regs *regs) { irqentry_state_t state = irqentry_nmi_enter(regs); do_nmi_trap(); irqentry_nmi_exit(regs, state); } -- Best Regards Guo Ren