From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 445E5C77B7E for ; Mon, 29 May 2023 01:20:04 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0DEFB847C1; Mon, 29 May 2023 03:20:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="GjbFStws"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 550E3847D5; Mon, 29 May 2023 03:19:58 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6632780181 for ; Mon, 29 May 2023 03:19:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=guoren@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7A75E61F9B for ; Mon, 29 May 2023 01:19:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD2EEC433A0 for ; Mon, 29 May 2023 01:19:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685323189; bh=4UP1jlLcs/xKOefNQGKGhkXtq+FWA3x4VO0xzqJ7vHw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=GjbFStwsQ93Sk6ivme9KTLbf6M/Eumbkg76CrW3oRBDPdYxn6yIOgxodmYQtO9ZUg IGwKp4iChIGqrF6IbUW274/+KH+W1xHT5fy+gp/1YAd3ql9SR1a/YkKvCQM1mFoUCe OCcVRbWVzsRAmF/ui0+og/cLn0/TjyHd5zeVLLdtDuGi+AG2FdejsyclOmwhBwr9Wx gBUG6YrjSd+FwthSt9m7fQXkmp3i3C/s5GkTg3O1Z1SZADhOZVfEvAI0aot1gUuFA2 DHiKahgWJFKbLjkwGa30WNJjDoZA9aSKtfrKD676E0lpN8FQK2FWrAD0Td4WXs9c7k HRB5/YDBUEvUA== Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5149e65c244so516781a12.3 for ; Sun, 28 May 2023 18:19:49 -0700 (PDT) X-Gm-Message-State: AC+VfDxRqt1fE2+gcSLRkctxoUs4rQ0IBOihKbO/k+tCxGNoxq+XXEwU POenef56213fiZgwACEzrQ5wLiarZBybe0bQJN0= X-Google-Smtp-Source: ACHHUZ5m5KpZEB7EBIpKXmCTuLv3/aa/GXLOdZ7vNnKYW7XCRcC7wijJmpjh5jZfxIvE9finhC/Cz+sR8S9RCQnlpi0= X-Received: by 2002:aa7:d3cb:0:b0:510:e80f:fa4e with SMTP id o11-20020aa7d3cb000000b00510e80ffa4emr6278718edr.1.1685323187897; Sun, 28 May 2023 18:19:47 -0700 (PDT) MIME-Version: 1.0 References: <20230526124107.894-1-dlan@gentoo.org> <20230526124107.894-3-dlan@gentoo.org> In-Reply-To: From: Guo Ren Date: Mon, 29 May 2023 09:19:36 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RESEND PATCH v1 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board To: Yixun Lan Cc: u-boot@lists.denx.de, Rick Chen , Leo , Wei Fu , Jisheng Zhang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Sat, May 27, 2023 at 5:17=E2=80=AFPM Yixun Lan wrote: > > Hi Guo: > > On 09:43 Sat 27 May , Guo Ren wrote: > > Sorry, why we need dts here? If we put dts here, we could delete the > > one in Linux. > No, I think it's more than a historical reason for why we have two dts > both in u-boot and kernel. And this dts here is merely used by u-boot, > it could be a simplified version comparing to kernel's dts. > > > > > We shouldn't put it with two places, that would be bad for maintanice. > I can totally understand your concern, in fact, we are trying to keep the= m sync, > so I will probably wait the dts of kernel settle down, before take action= here. > so, please conside this patch as RFC, and may change in next revisions.. Thx for clarification. But I still concern the necessary of the patch, could you move this from this series first, because we've argument on it. Your other patches looks good, I'm looking forward your next v2. But for this one, let's talk it after kernel side merged. > > > > > On Fri, May 26, 2023 at 8:41=E2=80=AFPM Yixun Lan wro= te: > > > > > > Only add basic support for CPU, PLIC UART and Timer. > > > > > > Reviewed-by: Wei Fu > > > Signed-off-by: Yixun Lan > > > --- > > > arch/riscv/dts/Makefile | 1 + > > > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ > > > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ > > > arch/riscv/dts/th1520.dtsi | 435 ++++++++++++++++++= ++ > > > 4 files changed, 502 insertions(+) > > > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts > > > create mode 100644 arch/riscv/dts/th1520.dtsi > > > > > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > > > index 79a58694f5..72fd815a40 100644 > > > --- a/arch/riscv/dts/Makefile > > > +++ b/arch/riscv/dts/Makefile > > > @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) +=3D hifive-unm= atched-a00.dtb > > > dtb-$(CONFIG_TARGET_SIPEED_MAIX) +=3D k210-maix-bit.dtb > > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=3D jh7110-starfive-visio= nfive-2-v1.3b.dtb > > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=3D jh7110-starfive-visio= nfive-2-v1.2a.dtb > > > +dtb-$(CONFIG_TARGET_TH1520_LPI4A) +=3D th1520-lichee-pi-4a.dtb > > > include $(srctree)/scripts/Makefile.dts > > > > > > targets +=3D $(dtb-y) > > > diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv= /dts/th1520-lichee-module-4a.dtsi > > > new file mode 100644 > > > index 0000000000..dc00e3dfa0 > > > --- /dev/null > > > +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > @@ -0,0 +1,34 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Copyright (C) 2023 Jisheng Zhang > > > + */ > > > + > > > +/dts-v1/; > > > + > > > +#include "th1520.dtsi" > > > + > > > +/ { > > > + model =3D "Sipeed Lichee Module 4A"; > > > + compatible =3D "sipeed,lichee-module-4a", "thead,th1520"; > > > + > > > + memory@0 { > > > + device_type =3D "memory"; > > > + reg =3D <0x0 0x00000000 0x2 0x00000000>; > > > + }; > > > +}; > > > + > > > +&osc { > > > + clock-frequency =3D <24000000>; > > > +}; > > > + > > > +&osc_32k { > > > + clock-frequency =3D <32768>; > > > +}; > > > + > > > +&apb_clk { > > > + clock-frequency =3D <62500000>; > > > +}; > > > + > > > +&uart_sclk { > > > + clock-frequency =3D <100000000>; > > > +}; > > > diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/= th1520-lichee-pi-4a.dts > > > new file mode 100644 > > > index 0000000000..a1248b2ee3 > > > --- /dev/null > > > +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts > > > @@ -0,0 +1,32 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Copyright (C) 2023 Jisheng Zhang > > > + */ > > > + > > > +#include "th1520-lichee-module-4a.dtsi" > > > + > > > +/ { > > > + model =3D "Sipeed Lichee Pi 4A"; > > > + compatible =3D "sipeed,lichee-pi-4a", "sipeed,lichee-module-4= a", "thead,th1520"; > > > + > > > + aliases { > > > + gpio0 =3D &gpio0; > > > + gpio1 =3D &gpio1; > > > + gpio2 =3D &gpio2; > > > + gpio3 =3D &gpio3; > > > + serial0 =3D &uart0; > > > + serial1 =3D &uart1; > > > + serial2 =3D &uart2; > > > + serial3 =3D &uart3; > > > + serial4 =3D &uart4; > > > + serial5 =3D &uart5; > > > + }; > > > + > > > + chosen { > > > + stdout-path =3D "serial0:115200n8"; > > > + }; > > > +}; > > > + > > > +&uart0 { > > > + status =3D "okay"; > > > +}; > > > diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi > > > new file mode 100644 > > > index 0000000000..f62a62da6e > > > --- /dev/null > > > +++ b/arch/riscv/dts/th1520.dtsi > > > @@ -0,0 +1,435 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Copyright (C) 2021 Alibaba Group Holding Limited. > > > + * Copyright (C) 2023 Jisheng Zhang > > > + */ > > > + > > > +#include > > > + > > > +/ { > > > + compatible =3D "thead,th1520"; > > > + #address-cells =3D <2>; > > > + #size-cells =3D <2>; > > > + > > > + cpus: cpus { > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + timebase-frequency =3D <3000000>; > > > + > > > + c910_0: cpu@0 { > > > + compatible =3D "thead,c910", "riscv"; > > > + device_type =3D "cpu"; > > > + riscv,isa =3D "rv64imafdc"; > > > + reg =3D <0>; > > > + i-cache-block-size =3D <64>; > > > + i-cache-size =3D <65536>; > > > + i-cache-sets =3D <512>; > > > + d-cache-block-size =3D <64>; > > > + d-cache-size =3D <65536>; > > > + d-cache-sets =3D <512>; > > > + next-level-cache =3D <&l2_cache>; > > > + mmu-type =3D "riscv,sv39"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #interrupt-cells =3D <1>; > > > + }; > > > + }; > > > + > > > + c910_1: cpu@1 { > > > + compatible =3D "thead,c910", "riscv"; > > > + device_type =3D "cpu"; > > > + riscv,isa =3D "rv64imafdc"; > > > + reg =3D <1>; > > > + i-cache-block-size =3D <64>; > > > + i-cache-size =3D <65536>; > > > + i-cache-sets =3D <512>; > > > + d-cache-block-size =3D <64>; > > > + d-cache-size =3D <65536>; > > > + d-cache-sets =3D <512>; > > > + next-level-cache =3D <&l2_cache>; > > > + mmu-type =3D "riscv,sv39"; > > > + > > > + cpu1_intc: interrupt-controller { > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #interrupt-cells =3D <1>; > > > + }; > > > + }; > > > + > > > + c910_2: cpu@2 { > > > + compatible =3D "thead,c910", "riscv"; > > > + device_type =3D "cpu"; > > > + riscv,isa =3D "rv64imafdc"; > > > + reg =3D <2>; > > > + i-cache-block-size =3D <64>; > > > + i-cache-size =3D <65536>; > > > + i-cache-sets =3D <512>; > > > + d-cache-block-size =3D <64>; > > > + d-cache-size =3D <65536>; > > > + d-cache-sets =3D <512>; > > > + next-level-cache =3D <&l2_cache>; > > > + mmu-type =3D "riscv,sv39"; > > > + > > > + cpu2_intc: interrupt-controller { > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #interrupt-cells =3D <1>; > > > + }; > > > + }; > > > + > > > + c910_3: cpu@3 { > > > + compatible =3D "thead,c910", "riscv"; > > > + device_type =3D "cpu"; > > > + riscv,isa =3D "rv64imafdc"; > > > + reg =3D <3>; > > > + i-cache-block-size =3D <64>; > > > + i-cache-size =3D <65536>; > > > + i-cache-sets =3D <512>; > > > + d-cache-block-size =3D <64>; > > > + d-cache-size =3D <65536>; > > > + d-cache-sets =3D <512>; > > > + next-level-cache =3D <&l2_cache>; > > > + mmu-type =3D "riscv,sv39"; > > > + > > > + cpu3_intc: interrupt-controller { > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #interrupt-cells =3D <1>; > > > + }; > > > + }; > > > + > > > + cpu-map { > > > + cluster0 { > > > + core0 { > > > + cpu =3D <&c910_0>; > > > + }; > > > + > > > + core1 { > > > + cpu =3D <&c910_1>; > > > + }; > > > + > > > + core2 { > > > + cpu =3D <&c910_2>; > > > + }; > > > + > > > + core3 { > > > + cpu =3D <&c910_3>; > > > + }; > > > + }; > > > + }; > > > + > > > + l2_cache: l2-cache { > > > + compatible =3D "cache"; > > > + cache-block-size =3D <64>; > > > + cache-level =3D <2>; > > > + cache-size =3D <1048576>; > > > + cache-sets =3D <1024>; > > > + cache-unified; > > > + }; > > > + }; > > > + > > > + osc: oscillator { > > > + compatible =3D "fixed-clock"; > > > + clock-output-names =3D "osc_24m"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > + osc_32k: 32k-oscillator { > > > + compatible =3D "fixed-clock"; > > > + clock-output-names =3D "osc_32k"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > + apb_clk: apb-clk-clock { > > > + compatible =3D "fixed-clock"; > > > + clock-output-names =3D "apb_clk"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > + uart_sclk: uart-sclk-clock { > > > + compatible =3D "fixed-clock"; > > > + clock-output-names =3D "uart_sclk"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > + soc { > > > + compatible =3D "simple-bus"; > > > + interrupt-parent =3D <&plic>; > > > + #address-cells =3D <2>; > > > + #size-cells =3D <2>; > > > + ranges; > > > + > > > + cpurst: cpurst { > > > + compatible =3D "thead,reset-th1520"; > > > + entry-reg =3D <0xff 0xff019050>; > > > + entry-cnt =3D <4>; > > > + control-reg =3D <0xff 0xff015004>; > > > + control-val =3D <0x1c>; > > > + csr-copy =3D <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0= x7c5 0x7cc>; > > > + }; > > This part has been changed. > > > noted, will update accordingly > > > > + > > > + plic: interrupt-controller@ffd8000000 { > > > + compatible =3D "thead,th1520-plic", "thead,c9= 00-plic"; > > > + reg =3D <0xff 0xd8000000 0x0 0x01000000>; > > > + interrupts-extended =3D <&cpu0_intc 11>, <&cp= u0_intc 9>, > > > + <&cpu1_intc 11>, <&cpu1= _intc 9>, > > > + <&cpu2_intc 11>, <&cpu2= _intc 9>, > > > + <&cpu3_intc 11>, <&cpu3= _intc 9>; > > > + interrupt-controller; > > > + #address-cells =3D <0>; > > > + #interrupt-cells =3D <2>; > > > + riscv,ndev =3D <240>; > > > + }; > > > + > > > + clint: timer@ffdc000000 { > > > + compatible =3D "thead,th1520-clint", "thead,c= 900-clint"; > > > + reg =3D <0xff 0xdc000000 0x0 0x00010000>; > > > + interrupts-extended =3D <&cpu0_intc 3>, <&cpu= 0_intc 7>, > > > + <&cpu1_intc 3>, <&cpu1_= intc 7>, > > > + <&cpu2_intc 3>, <&cpu2_= intc 7>, > > > + <&cpu3_intc 3>, <&cpu3_= intc 7>; > > > + }; > > > + > > > + uart0: serial@ffe7014000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0xff 0xe7014000 0x0 0x4000>; > > > + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&uart_sclk>; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + uart1: serial@ffe7f00000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0xff 0xe7f00000 0x0 0x4000>; > > > + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&uart_sclk>; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + uart3: serial@ffe7f04000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0xff 0xe7f04000 0x0 0x4000>; > > > + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&uart_sclk>; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + gpio2: gpio@ffe7f34000 { > > > + compatible =3D "snps,dw-apb-gpio"; > > > + reg =3D <0xff 0xe7f34000 0x0 0x1000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + portc: gpio-controller@0 { > > > + compatible =3D "snps,dw-apb-gpio-port= "; > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + ngpios =3D <32>; > > > + reg =3D <0>; > > > + interrupt-controller; > > > + #interrupt-cells =3D <2>; > > > + interrupts =3D <58 IRQ_TYPE_LEVEL_HIG= H>; > > > + }; > > > + }; > > > + > > > + gpio3: gpio@ffe7f38000 { > > > + compatible =3D "snps,dw-apb-gpio"; > > > + reg =3D <0xff 0xe7f38000 0x0 0x1000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + portd: gpio-controller@0 { > > > + compatible =3D "snps,dw-apb-gpio-port= "; > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + ngpios =3D <32>; > > > + reg =3D <0>; > > > + interrupt-controller; > > > + #interrupt-cells =3D <2>; > > > + interrupts =3D <59 IRQ_TYPE_LEVEL_HIG= H>; > > > + }; > > > + }; > > > + > > > + gpio0: gpio@ffec005000 { > > > + compatible =3D "snps,dw-apb-gpio"; > > > + reg =3D <0xff 0xec005000 0x0 0x1000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + porta: gpio-controller@0 { > > > + compatible =3D "snps,dw-apb-gpio-port= "; > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + ngpios =3D <32>; > > > + reg =3D <0>; > > > + interrupt-controller; > > > + #interrupt-cells =3D <2>; > > > + interrupts =3D <56 IRQ_TYPE_LEVEL_HIG= H>; > > > + }; > > > + }; > > > + > > > + gpio1: gpio@ffec006000 { > > > + compatible =3D "snps,dw-apb-gpio"; > > > + reg =3D <0xff 0xec006000 0x0 0x1000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + portb: gpio-controller@0 { > > > + compatible =3D "snps,dw-apb-gpio-port= "; > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + ngpios =3D <32>; > > > + reg =3D <0>; > > > + interrupt-controller; > > > + #interrupt-cells =3D <2>; > > > + interrupts =3D <57 IRQ_TYPE_LEVEL_HIG= H>; > > > + }; > > > + }; > > > + > > > + uart2: serial@ffec010000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0xff 0xec010000 0x0 0x4000>; > > > + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&uart_sclk>; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer0: timer@ffefc32000 { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xefc32000 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer1: timer@ffefc32014 { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xefc32014 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer2: timer@ffefc32028 { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xefc32028 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer3: timer@ffefc3203c { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xefc3203c 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + uart4: serial@fff7f08000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0xff 0xf7f08000 0x0 0x4000>; > > > + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&uart_sclk>; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + uart5: serial@fff7f0c000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0xff 0xf7f0c000 0x0 0x4000>; > > > + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&uart_sclk>; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer4: timer@ffffc33000 { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xffc33000 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer5: timer@ffffc33014 { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xffc33014 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer6: timer@ffffc33028 { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xffc33028 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + timer7: timer@ffffc3303c { > > > + compatible =3D "snps,dw-apb-timer"; > > > + reg =3D <0xff 0xffc3303c 0x0 0x14>; > > > + clocks =3D <&apb_clk>; > > > + clock-names =3D "timer"; > > > + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + ao_gpio0: gpio@fffff41000 { > > > + compatible =3D "snps,dw-apb-gpio"; > > > + reg =3D <0xff 0xfff41000 0x0 0x1000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + porte: gpio-controller@0 { > > > + compatible =3D "snps,dw-apb-gpio-port= "; > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + ngpios =3D <32>; > > > + reg =3D <0>; > > > + interrupt-controller; > > > + #interrupt-cells =3D <2>; > > > + interrupts =3D <76 IRQ_TYPE_LEVEL_HIG= H>; > > > + }; > > > + }; > > > + > > > + ao_gpio1: gpio@fffff52000 { > > > + compatible =3D "snps,dw-apb-gpio"; > > > + reg =3D <0xff 0xfff52000 0x0 0x1000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + portf: gpio-controller@0 { > > > + compatible =3D "snps,dw-apb-gpio-port= "; > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + ngpios =3D <32>; > > > + reg =3D <0>; > > > + interrupt-controller; > > > + #interrupt-cells =3D <2>; > > > + interrupts =3D <55 IRQ_TYPE_LEVEL_HIG= H>; > > > + }; > > > + }; > > > + }; > > > +}; > > > -- > > > 2.40.0 > > > > > > > > > -- > > Best Regards > > Guo Ren > > -- > Yixun Lan (dlan) > Gentoo Linux Developer > GPG Key ID AABEFD55 --=20 Best Regards Guo Ren