From: Guo Ren <guoren@kernel.org> To: Chen Zhongjin <chenzhongjin@huawei.com> Cc: arnd@arndb.de, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, palmer@dabbelt.com, paul.walmsley@sifive.com, mark.rutland@arm.com, zouyipeng@huawei.com, bigeasy@linutronix.de, David.Laight@aculab.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com> Subject: Re: [PATCH V5 08/11] riscv: Support HAVE_IRQ_EXIT_ON_IRQ_STACK Date: Thu, 22 Sep 2022 09:26:37 +0800 [thread overview] Message-ID: <CAJF2gTSZmqW-KnL5oFrCMsf+FSyqn=W6GCtPs6983e26it8Qug@mail.gmail.com> (raw) In-Reply-To: <df9590bc-1a61-28c0-55eb-9f9539d03144@huawei.com> On Wed, Sep 21, 2022 at 7:56 PM Chen Zhongjin <chenzhongjin@huawei.com> wrote: > > Hi, > > Sorry to bother again, I just finished the test with your patches on > mine patch set. > > On 2022/9/21 17:53, Guo Ren wrote: > > On Wed, Sep 21, 2022 at 4:34 PM Chen Zhongjin <chenzhongjin@huawei.com> wrote: > >> Hi, > >> > >> On 2022/9/18 23:52, guoren@kernel.org wrote: > >>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > >>> index 5f49517cd3a2..426529b84db0 100644 > >>> --- a/arch/riscv/kernel/entry.S > >>> +++ b/arch/riscv/kernel/entry.S > >>> @@ -332,6 +332,33 @@ ENTRY(ret_from_kernel_thread) > >>> tail syscall_exit_to_user_mode > >>> ENDPROC(ret_from_kernel_thread) > >>> > >>> +#ifdef CONFIG_IRQ_STACKS > >>> +ENTRY(call_on_stack) > >>> + /* Create a frame record to save our ra and fp */ > >>> + addi sp, sp, -RISCV_SZPTR > >>> + REG_S ra, (sp) > >>> + addi sp, sp, -RISCV_SZPTR > >>> + REG_S fp, (sp) > >>> + > >>> + /* Save sp in fp */ > >>> + move fp, sp > >>> + > > Considering that s0 points to previous sp normally, I think here we > should have 'addi fp, sp, 2*RISCV_SZPTR'. > > An example below: > > addi sp, sp, -16 > sd ra, 8(sp) > sd s0, 0(sp) > addi s0, sp, 16 <- s0 is set to previous sp > ... > > ld ra,8(sp) > ld s0,0(sp) > addi sp,sp,16 > > So maybe it's better to save the stack frame as below: > > addi sp, sp, -2*RISCV_SZPTR > REG_S ra, RISCV_SZPTR(sp) > REG_S s0, (sp) > > /* Save sp in fp */ > addi s0, sp, 2*RISCV_SZPTR > > ... > > /* > * Restore sp from prev fp, and fp, ra from the frame > */ > addi sp, s0, -2*RISCV_SZPTR > REG_L ra, RISCV_SZPTR(sp) > REG_L s0, (sp) > addi sp, sp, 2*RISCV_SZPTR > > > Anyway, lets set fp as sp + 2 * RISCV_SZPTR, so that unwinder can > connect two stacks same as normal function. > > I tested this with my patch and the unwinder works properly. Thx, you got it. My patch broke the fp chain. I would fix it in the next version. > > > Thanks for your time! > > Best, > > Chen > > >>> + /* Move to the new stack and call the function there */ > >>> + li a3, IRQ_STACK_SIZE > >>> + add sp, a1, a3 > >>> + jalr a2 > >>> + > >>> + /* > >>> + * Restore sp from prev fp, and fp, ra from the frame > >>> + */ > >>> + move sp, fp > >>> + REG_L fp, (sp) > >>> + addi sp, sp, RISCV_SZPTR > >>> + REG_L ra, (sp) > >>> + addi sp, sp, RISCV_SZPTR > >>> + ret > >>> +ENDPROC(call_on_stack) > >>> +#endif > >> Seems my compiler (riscv64-linux-gnu-gcc 8.4.0, cross compiling from > >> x86) cannot recognize the register `fp`. > > The whole entry.S uses s0 instead of fp, so I approve of your advice. Thx. > > > >> After I changed it to `s0` this can pass compiling. > >> > >> > >> Seems there is nowhere else using `fp`, can this just using `s0` instead? > >> > >> Best, > >> > >> Chen > >> > >> -- Best Regards Guo Ren
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: Chen Zhongjin <chenzhongjin@huawei.com> Cc: arnd@arndb.de, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, palmer@dabbelt.com, paul.walmsley@sifive.com, mark.rutland@arm.com, zouyipeng@huawei.com, bigeasy@linutronix.de, David.Laight@aculab.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com> Subject: Re: [PATCH V5 08/11] riscv: Support HAVE_IRQ_EXIT_ON_IRQ_STACK Date: Thu, 22 Sep 2022 09:26:37 +0800 [thread overview] Message-ID: <CAJF2gTSZmqW-KnL5oFrCMsf+FSyqn=W6GCtPs6983e26it8Qug@mail.gmail.com> (raw) In-Reply-To: <df9590bc-1a61-28c0-55eb-9f9539d03144@huawei.com> On Wed, Sep 21, 2022 at 7:56 PM Chen Zhongjin <chenzhongjin@huawei.com> wrote: > > Hi, > > Sorry to bother again, I just finished the test with your patches on > mine patch set. > > On 2022/9/21 17:53, Guo Ren wrote: > > On Wed, Sep 21, 2022 at 4:34 PM Chen Zhongjin <chenzhongjin@huawei.com> wrote: > >> Hi, > >> > >> On 2022/9/18 23:52, guoren@kernel.org wrote: > >>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > >>> index 5f49517cd3a2..426529b84db0 100644 > >>> --- a/arch/riscv/kernel/entry.S > >>> +++ b/arch/riscv/kernel/entry.S > >>> @@ -332,6 +332,33 @@ ENTRY(ret_from_kernel_thread) > >>> tail syscall_exit_to_user_mode > >>> ENDPROC(ret_from_kernel_thread) > >>> > >>> +#ifdef CONFIG_IRQ_STACKS > >>> +ENTRY(call_on_stack) > >>> + /* Create a frame record to save our ra and fp */ > >>> + addi sp, sp, -RISCV_SZPTR > >>> + REG_S ra, (sp) > >>> + addi sp, sp, -RISCV_SZPTR > >>> + REG_S fp, (sp) > >>> + > >>> + /* Save sp in fp */ > >>> + move fp, sp > >>> + > > Considering that s0 points to previous sp normally, I think here we > should have 'addi fp, sp, 2*RISCV_SZPTR'. > > An example below: > > addi sp, sp, -16 > sd ra, 8(sp) > sd s0, 0(sp) > addi s0, sp, 16 <- s0 is set to previous sp > ... > > ld ra,8(sp) > ld s0,0(sp) > addi sp,sp,16 > > So maybe it's better to save the stack frame as below: > > addi sp, sp, -2*RISCV_SZPTR > REG_S ra, RISCV_SZPTR(sp) > REG_S s0, (sp) > > /* Save sp in fp */ > addi s0, sp, 2*RISCV_SZPTR > > ... > > /* > * Restore sp from prev fp, and fp, ra from the frame > */ > addi sp, s0, -2*RISCV_SZPTR > REG_L ra, RISCV_SZPTR(sp) > REG_L s0, (sp) > addi sp, sp, 2*RISCV_SZPTR > > > Anyway, lets set fp as sp + 2 * RISCV_SZPTR, so that unwinder can > connect two stacks same as normal function. > > I tested this with my patch and the unwinder works properly. Thx, you got it. My patch broke the fp chain. I would fix it in the next version. > > > Thanks for your time! > > Best, > > Chen > > >>> + /* Move to the new stack and call the function there */ > >>> + li a3, IRQ_STACK_SIZE > >>> + add sp, a1, a3 > >>> + jalr a2 > >>> + > >>> + /* > >>> + * Restore sp from prev fp, and fp, ra from the frame > >>> + */ > >>> + move sp, fp > >>> + REG_L fp, (sp) > >>> + addi sp, sp, RISCV_SZPTR > >>> + REG_L ra, (sp) > >>> + addi sp, sp, RISCV_SZPTR > >>> + ret > >>> +ENDPROC(call_on_stack) > >>> +#endif > >> Seems my compiler (riscv64-linux-gnu-gcc 8.4.0, cross compiling from > >> x86) cannot recognize the register `fp`. > > The whole entry.S uses s0 instead of fp, so I approve of your advice. Thx. > > > >> After I changed it to `s0` this can pass compiling. > >> > >> > >> Seems there is nowhere else using `fp`, can this just using `s0` instead? > >> > >> Best, > >> > >> Chen > >> > >> -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-22 1:26 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-18 15:52 [PATCH V5 00/11] riscv: Add GENERIC_ENTRY support and related features guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 01/11] riscv: elf_kexec: Fixup compile warning guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 02/11] riscv: compat_syscall_table: " guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 03/11] riscv: ptrace: Remove duplicate operation guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 04/11] compiler_types.h: Add __noinstr_section() for noinstr guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 05/11] riscv: traps: Add noinstr to prevent instrumentation inserted guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 06/11] entry: Prevent DEBUG_PREEMPT warning guoren 2022-09-18 15:52 ` guoren 2022-09-19 11:58 ` Peter Zijlstra 2022-09-19 11:58 ` Peter Zijlstra 2022-09-20 1:45 ` Guo Ren 2022-09-20 1:45 ` Guo Ren 2022-09-30 12:27 ` Guo Ren 2022-09-30 12:27 ` Guo Ren 2022-09-18 15:52 ` [PATCH V5 07/11] riscv: convert to generic entry guoren 2022-09-18 15:52 ` guoren 2022-09-19 13:34 ` Peter Zijlstra 2022-09-19 13:34 ` Peter Zijlstra 2022-09-20 6:36 ` Guo Ren 2022-09-20 6:36 ` Guo Ren 2022-09-20 7:22 ` Peter Zijlstra 2022-09-20 7:22 ` Peter Zijlstra 2022-09-30 11:28 ` Guo Ren 2022-09-30 11:28 ` Guo Ren 2022-09-18 15:52 ` [PATCH V5 08/11] riscv: Support HAVE_IRQ_EXIT_ON_IRQ_STACK guoren 2022-09-18 15:52 ` guoren 2022-09-19 13:45 ` Peter Zijlstra 2022-09-19 13:45 ` Peter Zijlstra 2022-09-20 6:08 ` Guo Ren 2022-09-20 6:08 ` Guo Ren 2022-09-20 7:27 ` Peter Zijlstra 2022-09-20 7:27 ` Peter Zijlstra 2022-09-20 7:34 ` Peter Zijlstra 2022-09-20 7:34 ` Peter Zijlstra 2022-09-21 6:16 ` Guo Ren 2022-09-21 6:16 ` Guo Ren 2022-09-21 8:34 ` Chen Zhongjin 2022-09-21 8:34 ` Chen Zhongjin 2022-09-21 9:53 ` Guo Ren 2022-09-21 9:53 ` Guo Ren 2022-09-21 11:56 ` Chen Zhongjin 2022-09-21 11:56 ` Chen Zhongjin 2022-09-22 1:26 ` Guo Ren [this message] 2022-09-22 1:26 ` Guo Ren 2022-09-18 15:52 ` [PATCH V5 09/11] riscv: Support HAVE_SOFTIRQ_ON_OWN_STACK guoren 2022-09-18 15:52 ` guoren 2022-09-20 0:11 ` Guo Ren 2022-09-20 0:11 ` Guo Ren 2022-09-18 15:52 ` [PATCH V5 10/11] riscv: Add config of thread stack size guoren 2022-09-18 15:52 ` guoren 2022-09-18 15:52 ` [PATCH V5 11/11] riscv: Add support for STACKLEAK gcc plugin guoren 2022-09-18 15:52 ` guoren
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