From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F00CDC433F5 for ; Mon, 17 Jan 2022 07:26:47 +0000 (UTC) Received: from localhost ([::1]:50394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9MPe-00011J-Tq for qemu-devel@archiver.kernel.org; Mon, 17 Jan 2022 02:26:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9MIL-000740-LW; Mon, 17 Jan 2022 02:19:16 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:48534) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9MI6-0000ic-8s; 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Sun, 16 Jan 2022 23:18:51 -0800 (PST) X-Gm-Message-State: AOAM532fugMv5/RWQj07TRQuRCgCrSjypp9nM6pbYF84jyEzqxB5ykqA P0Y8X0naxWoPNID9uiBe6SNCvCFKDaAKoZEvNjk= X-Google-Smtp-Source: ABdhPJzcZPjL8sDn1EMcl24tIWpRG286vWEe0rhs4iD/nl6EFNpLP/o59mXD2tTu+XEeuPAdZTWKxmwoEPNJZiWBZ6c= X-Received: by 2002:ac5:cbc8:: with SMTP id h8mr5583130vkn.8.1642403930431; Sun, 16 Jan 2022 23:18:50 -0800 (PST) MIME-Version: 1.0 References: <20220116025925.29973-1-liweiwei@iscas.ac.cn> <20220116025925.29973-5-liweiwei@iscas.ac.cn> In-Reply-To: <20220116025925.29973-5-liweiwei@iscas.ac.cn> From: Guo Ren Date: Mon, 17 Jan 2022 15:18:39 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension To: Weiwei Li Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=145.40.68.75; envelope-from=guoren@kernel.org; helo=ams.source.kernel.org X-Spam_score_int: -77 X-Spam_score: -7.8 X-Spam_bar: ------- X-Spam_report: (-7.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.699, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , "open list:RISC-V" , Anup Patel , Wang Junqiang , bin.meng@windriver.com, "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li wrote: > > - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently > - add PTE_PBMT bits check for inner PTE > - add reserved bits check for all PTE > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Tested-by: Heiko Stuebner > Reviewed-by: Anup Patel > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_helper.c | 8 ++++++-- > 4 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 45ac98e06b..4f82bd00a3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c3d1845ca1..53f314c752 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -329,6 +329,7 @@ struct RISCVCPU { > bool ext_icsr; > bool ext_svinval; > bool ext_svnapot; > + bool ext_svpbmt; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index bc23e3b523..ee294c1d0b 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -486,7 +486,10 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ > +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ > #define PTE_N 0x8000000000000000 /* NAPOT translation */ > +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 832a2dd79c..f90766e026 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -619,17 +619,21 @@ restart: > return TRANSLATE_FAIL; > } > > - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; > + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; This would break rv32. Please ref: https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/ > > RISCVCPU *cpu = env_archcpu(env); > if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { > return TRANSLATE_FAIL; > + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { > + return TRANSLATE_FAIL; > + } else if (pte & PTE_RSVD) { > + return TRANSLATE_FAIL; > } else if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > /* Inner PTE, continue walking */ > - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) { > + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { > return TRANSLATE_FAIL; > } > base = ppn << PGSHIFT; > -- > 2.17.1 > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1n9MIh-000770-3O for mharc-qemu-riscv@gnu.org; Mon, 17 Jan 2022 02:19:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9MIL-000740-LW; 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Sun, 16 Jan 2022 23:18:51 -0800 (PST) X-Gm-Message-State: AOAM532fugMv5/RWQj07TRQuRCgCrSjypp9nM6pbYF84jyEzqxB5ykqA P0Y8X0naxWoPNID9uiBe6SNCvCFKDaAKoZEvNjk= X-Google-Smtp-Source: ABdhPJzcZPjL8sDn1EMcl24tIWpRG286vWEe0rhs4iD/nl6EFNpLP/o59mXD2tTu+XEeuPAdZTWKxmwoEPNJZiWBZ6c= X-Received: by 2002:ac5:cbc8:: with SMTP id h8mr5583130vkn.8.1642403930431; Sun, 16 Jan 2022 23:18:50 -0800 (PST) MIME-Version: 1.0 References: <20220116025925.29973-1-liweiwei@iscas.ac.cn> <20220116025925.29973-5-liweiwei@iscas.ac.cn> In-Reply-To: <20220116025925.29973-5-liweiwei@iscas.ac.cn> From: Guo Ren Date: Mon, 17 Jan 2022 15:18:39 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension To: Weiwei Li Cc: Anup Patel , Palmer Dabbelt , Alistair Francis , bin.meng@windriver.com, "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Wang Junqiang , =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=145.40.68.75; envelope-from=guoren@kernel.org; helo=ams.source.kernel.org X-Spam_score_int: -77 X-Spam_score: -7.8 X-Spam_bar: ------- X-Spam_report: (-7.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.699, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Jan 2022 07:19:27 -0000 On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li wrote: > > - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently > - add PTE_PBMT bits check for inner PTE > - add reserved bits check for all PTE > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Tested-by: Heiko Stuebner > Reviewed-by: Anup Patel > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_helper.c | 8 ++++++-- > 4 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 45ac98e06b..4f82bd00a3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c3d1845ca1..53f314c752 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -329,6 +329,7 @@ struct RISCVCPU { > bool ext_icsr; > bool ext_svinval; > bool ext_svnapot; > + bool ext_svpbmt; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index bc23e3b523..ee294c1d0b 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -486,7 +486,10 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ > +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ > #define PTE_N 0x8000000000000000 /* NAPOT translation */ > +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 832a2dd79c..f90766e026 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -619,17 +619,21 @@ restart: > return TRANSLATE_FAIL; > } > > - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; > + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; This would break rv32. Please ref: https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/ > > RISCVCPU *cpu = env_archcpu(env); > if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { > return TRANSLATE_FAIL; > + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { > + return TRANSLATE_FAIL; > + } else if (pte & PTE_RSVD) { > + return TRANSLATE_FAIL; > } else if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > /* Inner PTE, continue walking */ > - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) { > + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { > return TRANSLATE_FAIL; > } > base = ppn << PGSHIFT; > -- > 2.17.1 > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/