From: Guo Ren <guoren@kernel.org>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Guo Ren <guoren@linux.alibaba.com>, Bin Meng <bmeng.cn@gmail.com>,
Xiang W <wxjstz@126.com>, Samuel Holland <samuel@sholland.org>,
Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Anup Patel <anup.patel@wdc.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
OpenSBI <opensbi@lists.infradead.org>
Subject: Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT
Date: Tue, 19 Oct 2021 14:10:19 +0800 [thread overview]
Message-ID: <CAJF2gTTjhc2JvC9xdXf6DagMNR_sg41txjnw5Wn2NfJLXd7woA@mail.gmail.com> (raw)
In-Reply-To: <20211015100941.17621-1-heinrich.schuchardt@canonical.com>
On Fri, Oct 15, 2021 at 6:10 PM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
>
> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to
> the MTIMER device. The current schema does not allow to specify this.
>
> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the
> restriction. Samuael Holland suggested in
> lib: utils/timer: Use standard property to specify 32-bit I/O
> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e
> to use "reg-io-width = <4>;" as the reg-io-width property is generally used
> in the devicetree schema for such a condition.
>
> A release candidate of the ACLINT specification is available at
> https://github.com/riscv/riscv-aclint/releases
>
> Add reg-io-width as optional property to the SiFive Core Local Interruptor.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a35952f48742..266012d887b5 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -41,6 +41,13 @@ properties:
> reg:
> maxItems: 1
>
> + reg-io-width:
> + description: |
> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support
^^^^^^^^^^^ -> allwinner d1, new version of our processors
would support 64bit access
> + 32bit access for MTIMER.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + const: 4
> +
> interrupts-extended:
> minItems: 1
>
> --
> 2.32.0
>
>
> --
> opensbi mailing list
> opensbi@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Guo Ren <guoren@linux.alibaba.com>,
Bin Meng <bmeng.cn@gmail.com>, Xiang W <wxjstz@126.com>,
Samuel Holland <samuel@sholland.org>,
Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Anup Patel <anup.patel@wdc.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
OpenSBI <opensbi@lists.infradead.org>
Subject: Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT
Date: Tue, 19 Oct 2021 14:10:19 +0800 [thread overview]
Message-ID: <CAJF2gTTjhc2JvC9xdXf6DagMNR_sg41txjnw5Wn2NfJLXd7woA@mail.gmail.com> (raw)
In-Reply-To: <20211015100941.17621-1-heinrich.schuchardt@canonical.com>
On Fri, Oct 15, 2021 at 6:10 PM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
>
> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to
> the MTIMER device. The current schema does not allow to specify this.
>
> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the
> restriction. Samuael Holland suggested in
> lib: utils/timer: Use standard property to specify 32-bit I/O
> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e
> to use "reg-io-width = <4>;" as the reg-io-width property is generally used
> in the devicetree schema for such a condition.
>
> A release candidate of the ACLINT specification is available at
> https://github.com/riscv/riscv-aclint/releases
>
> Add reg-io-width as optional property to the SiFive Core Local Interruptor.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a35952f48742..266012d887b5 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -41,6 +41,13 @@ properties:
> reg:
> maxItems: 1
>
> + reg-io-width:
> + description: |
> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support
^^^^^^^^^^^ -> allwinner d1, new version of our processors
would support 64bit access
> + 32bit access for MTIMER.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + const: 4
> +
> interrupts-extended:
> minItems: 1
>
> --
> 2.32.0
>
>
> --
> opensbi mailing list
> opensbi@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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next prev parent reply other threads:[~2021-10-19 6:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 10:09 [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT Heinrich Schuchardt
2021-10-15 10:09 ` Heinrich Schuchardt
2021-10-15 10:14 ` Bin Meng
2021-10-15 10:14 ` Bin Meng
2021-10-15 11:54 ` Heinrich Schuchardt
2021-10-15 11:54 ` Heinrich Schuchardt
2021-10-15 12:15 ` Jessica Clarke
2021-10-15 12:15 ` Jessica Clarke
2021-10-15 12:42 ` Heinrich Schuchardt
2021-10-15 12:42 ` Heinrich Schuchardt
2021-10-15 13:46 ` Bin Meng
2021-10-15 13:46 ` Bin Meng
2021-10-17 7:54 ` Xiang W
2021-10-17 7:54 ` Xiang W
2021-10-19 6:10 ` Guo Ren [this message]
2021-10-19 6:10 ` Guo Ren
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