From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75BA0C433F5 for ; Wed, 13 Oct 2021 00:48:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CBF760EDF for ; Wed, 13 Oct 2021 00:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235240AbhJMAuE (ORCPT ); Tue, 12 Oct 2021 20:50:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:38786 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234265AbhJMAuD (ORCPT ); Tue, 12 Oct 2021 20:50:03 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D25D660EDF for ; Wed, 13 Oct 2021 00:48:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634086080; bh=a6HAceh2igYZ/jHxri/gKKRe+lR1pmv01NNdtrqIyGY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=mLX8E04C7L4HGCzGqu639GlpJmRrd1wcJtrYvlHfM72UJu7yTwlYggsxJSDdxB32c eRzy2FQWSx87AhMoBjYCMCOtr3ApW0ozKXPOHLnzcPDUiNELIZDHeqLl7AyrSpzngR /T60PvKvmdnwVrWwCh1iA6/dHW6/BrcCi/+smbU/koEvlZX7J5zgmLRD7rWqk2iKtd wjwOOkfQgRmTDvQHhLoI9m4Xxr0SKVGJMDxQCvSOKpkH3QJVWYbJRbf/X1Fz+NN6gH iQaAjY3ryZBaANp5QH8Cd+SRNZVW49x9h0LSDJnkU/2+2l9c7/wY1Ba/hahm7W9yYN dPfoOQxBeoNGg== Received: by mail-vk1-f181.google.com with SMTP id l39so802811vkd.7 for ; Tue, 12 Oct 2021 17:48:00 -0700 (PDT) X-Gm-Message-State: AOAM5337tmDub5F8wS9s1XYU7vnUtCRCnfff4SwFBVtULGeHOnXxEJ5b ZB+bONCwctHV+J3ylmd7D5STQ4ANOg4IKgLCoHM= X-Google-Smtp-Source: ABdhPJwuAeXffmbONs1Dm69zu98tZn1ZPM4jYu8FThhRGYdQvURZeKDofJtl/UtQQNoUTDmqIukoBu7Zkg/YVcYLt/A= X-Received: by 2002:a67:c08d:: with SMTP id x13mr35590851vsi.43.1634086079921; Tue, 12 Oct 2021 17:47:59 -0700 (PDT) MIME-Version: 1.0 References: <20211012153432.2817285-1-guoren@kernel.org> <20211012153432.2817285-2-guoren@kernel.org> <4404316.9H8m7z83OK@diego> In-Reply-To: <4404316.9H8m7z83OK@diego> From: Guo Ren Date: Wed, 13 Oct 2021 08:47:48 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V2 2/2] irqchip/sifive-plic: Add thead,c9xx-plic support To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: linux-riscv , Atish Patra , Marc Zyngier , Thomas Gleixner , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Guo Ren , Anup Patel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 13, 2021 at 7:06 AM Heiko St=C3=BCbner wrote: > > Hi, > > Am Dienstag, 12. Oktober 2021, 18:40:26 CEST schrieb Anup Patel: > > On Tue, Oct 12, 2021 at 9:04 PM wrote: > > > > > > From: Guo Ren > > > > > > thead,c9xx-plic would mask IRQ with readl(claim), so it needn't > > > mask/unmask which needed in RISC-V PLIC. > > > > > > When in IRQS_ONESHOT & IRQCHIP_EOI_THREADED path, unnecessary mask > > > operation would cause a blocking irq bug in thead,c9xx-plic. Because > > > when IRQ is disabled in c9xx, writel(hwirq, claim) would be invalid. > > > > > > Signed-off-by: Guo Ren > > > Cc: Anup Patel > > > Cc: Thomas Gleixner > > > Cc: Marc Zyngier > > > Cc: Palmer Dabbelt > > > Cc: Atish Patra > > > > > > --- > > > > > > Changes since V2: > > > - Add a separate compatible string "thead,c9xx-plic" > > > - set irq_mask/unmask of "plic_chip" to NULL and point > > > irq_enable/disable of "plic_chip" to plic_irq_mask/unmask > > > - Add a detailed comment block in plic_init() about the > > > differences in Claim/Completion process of RISC-V PLIC and C9xx > > > PLIC. > > > --- > > > drivers/irqchip/irq-sifive-plic.c | 17 +++++++++++++++++ > > > 1 file changed, 17 insertions(+) > > > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-= sifive-plic.c > > > index cf74cfa82045..3756b1c147c3 100644 > > > --- a/drivers/irqchip/irq-sifive-plic.c > > > +++ b/drivers/irqchip/irq-sifive-plic.c > > > @@ -79,6 +79,7 @@ struct plic_handler { > > > }; > > > static int plic_parent_irq __ro_after_init; > > > static bool plic_cpuhp_setup_done __ro_after_init; > > > +static bool disable_mask_unmask __ro_after_init; > > > static DEFINE_PER_CPU(struct plic_handler, plic_handlers); > > > > > > static inline void plic_toggle(struct plic_handler *handler, > > > @@ -181,6 +182,13 @@ static int plic_irqdomain_map(struct irq_domain = *d, unsigned int irq, > > > { > > > struct plic_priv *priv =3D d->host_data; > > > > > > + if (disable_mask_unmask) { > > > + plic_chip.irq_mask =3D NULL; > > > + plic_chip.irq_unmask =3D NULL; > > > + plic_chip.irq_enable =3D plic_irq_unmask; > > > + plic_chip.irq_disable =3D plic_irq_mask; > > > + } > > > + > > > irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, > > > handle_fasteoi_irq, NULL, NULL); > > > irq_set_noprobe(irq); > > > @@ -390,5 +398,14 @@ static int __init plic_init(struct device_node *= node, > > > return error; > > > } > > > > > > +static int __init thead_c9xx_plic_init(struct device_node *node, > > > + struct device_node *parent) > > > +{ > > > + disable_mask_unmask =3D true; > > > > The plic_irqdomain_map() is called for each irq so "plic_chip" > > will be updated multiple times. > > > > You can drop the disable_mask_unmask variable and instead > > directly update "plic_chip" here. > > Actually I'd think something more dynamic might be appropriate? > > I.e. don't modify the generic plic_chip structure, but define a second > one for this type of chip and reference that one in plic_irqdomain_map > depending on the block found? > > According to [0] a system can have multiple PLICs and nothing > guarantees that they'll always be the same variant on future socs > [hardware engineers are very creative] > > So adding more stuff that modifies static content used by all PLICs > doesn't really improve driver quality here ;-) Agree, I like your style because it also could make cat /proc/interrupts name properly. static struct irq_chip sifive_plic_chip =3D { .name =3D "SiFive PLIC", static struct irq_chip thead_plic_chip =3D { .name =3D "T-HEAD PLIC", > > > Heiko > > > [0] https://lore.kernel.org/linux-riscv/1839bf9ef91de2358a7e8ecade361f7a@= www.loen.fr/T/ > > > > > > > + > > > + return plic_init(node, parent); > > > +} > > > + > > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > > > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legac= y systems */ > > > +IRQCHIP_DECLARE(thead_c9xx_plic, "thead,c9xx-plic", thead_c9xx_plic_= init); > > > -- > > > 2.25.1 > > > > > > > Regards, > > Anup > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > > > --=20 Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE7D6C433EF for ; Wed, 13 Oct 2021 00:48:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 99ABD610CB for ; Wed, 13 Oct 2021 00:48:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 99ABD610CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eloAJN94r7IlYslCXlbPrjK/+siCaclXb2SOoVC8D8U=; b=OfQDcIgnqccL26 E9NEhEt9GKubte5/CCHUx7xbvks/rDkXeRNQ5AFlHW2bktriclZal0wSjbVlvk6UbzWHIe83o0o/c agbnLZAzNPS7lrfeTkakAOfWmNBFQpRnX9B8vxZV3AouT54x0M9kon4e2CSyq8UOb8ws5vJIX2bqn 0yf1DJ9WDluqI6M7f7c72h0fh0WAWyv/TJhkBGqDfVunUxDTEv8x9Q65W87vLg8cW/QDigVc3WAj2 fv7mAf08bon6dBXC+S1kA/ciKNHsHYBzL5EfcAJ7wyu0RZJMWx0lpXXpD0fn59+qD6y43aeb0nCb1 uY9Tt/oyjkykUVP89jHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1maSRG-00EPod-H2; Wed, 13 Oct 2021 00:48:10 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1maSRD-00EPnW-IJ for linux-riscv@lists.infradead.org; Wed, 13 Oct 2021 00:48:09 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id CB56E60F11 for ; Wed, 13 Oct 2021 00:48:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634086080; bh=a6HAceh2igYZ/jHxri/gKKRe+lR1pmv01NNdtrqIyGY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=mLX8E04C7L4HGCzGqu639GlpJmRrd1wcJtrYvlHfM72UJu7yTwlYggsxJSDdxB32c eRzy2FQWSx87AhMoBjYCMCOtr3ApW0ozKXPOHLnzcPDUiNELIZDHeqLl7AyrSpzngR /T60PvKvmdnwVrWwCh1iA6/dHW6/BrcCi/+smbU/koEvlZX7J5zgmLRD7rWqk2iKtd wjwOOkfQgRmTDvQHhLoI9m4Xxr0SKVGJMDxQCvSOKpkH3QJVWYbJRbf/X1Fz+NN6gH iQaAjY3ryZBaANp5QH8Cd+SRNZVW49x9h0LSDJnkU/2+2l9c7/wY1Ba/hahm7W9yYN dPfoOQxBeoNGg== Received: by mail-vk1-f176.google.com with SMTP id o42so796152vkf.9 for ; Tue, 12 Oct 2021 17:48:00 -0700 (PDT) X-Gm-Message-State: AOAM531VRNS2da+BY4QJd9WOO1TxJTwl/ussoCI6rBQY8RBO3bGLiDZh 4sWYv1TNj/RnmVH+/KlTqN8hjpi2qtj5oo134DU= X-Google-Smtp-Source: ABdhPJwuAeXffmbONs1Dm69zu98tZn1ZPM4jYu8FThhRGYdQvURZeKDofJtl/UtQQNoUTDmqIukoBu7Zkg/YVcYLt/A= X-Received: by 2002:a67:c08d:: with SMTP id x13mr35590851vsi.43.1634086079921; Tue, 12 Oct 2021 17:47:59 -0700 (PDT) MIME-Version: 1.0 References: <20211012153432.2817285-1-guoren@kernel.org> <20211012153432.2817285-2-guoren@kernel.org> <4404316.9H8m7z83OK@diego> In-Reply-To: <4404316.9H8m7z83OK@diego> From: Guo Ren Date: Wed, 13 Oct 2021 08:47:48 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V2 2/2] irqchip/sifive-plic: Add thead,c9xx-plic support To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: linux-riscv , Atish Patra , Marc Zyngier , Thomas Gleixner , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Guo Ren , Anup Patel X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_174807_665625_4A490B77 X-CRM114-Status: GOOD ( 35.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gV2VkLCBPY3QgMTMsIDIwMjEgYXQgNzowNiBBTSBIZWlrbyBTdMO8Ym5lciA8aGVpa29Ac250 ZWNoLmRlPiB3cm90ZToKPgo+IEhpLAo+Cj4gQW0gRGllbnN0YWcsIDEyLiBPa3RvYmVyIDIwMjEs IDE4OjQwOjI2IENFU1Qgc2NocmllYiBBbnVwIFBhdGVsOgo+ID4gT24gVHVlLCBPY3QgMTIsIDIw MjEgYXQgOTowNCBQTSA8Z3VvcmVuQGtlcm5lbC5vcmc+IHdyb3RlOgo+ID4gPgo+ID4gPiBGcm9t OiBHdW8gUmVuIDxndW9yZW5AbGludXguYWxpYmFiYS5jb20+Cj4gPiA+Cj4gPiA+IHRoZWFkLGM5 eHgtcGxpYyB3b3VsZCBtYXNrIElSUSB3aXRoIHJlYWRsKGNsYWltKSwgc28gaXQgbmVlZG4ndAo+ ID4gPiBtYXNrL3VubWFzayB3aGljaCBuZWVkZWQgaW4gUklTQy1WIFBMSUMuCj4gPiA+Cj4gPiA+ IFdoZW4gaW4gSVJRU19PTkVTSE9UICYgSVJRQ0hJUF9FT0lfVEhSRUFERUQgcGF0aCwgdW5uZWNl c3NhcnkgbWFzawo+ID4gPiBvcGVyYXRpb24gd291bGQgY2F1c2UgYSBibG9ja2luZyBpcnEgYnVn IGluIHRoZWFkLGM5eHgtcGxpYy4gQmVjYXVzZQo+ID4gPiB3aGVuIElSUSBpcyBkaXNhYmxlZCBp biBjOXh4LCB3cml0ZWwoaHdpcnEsIGNsYWltKSB3b3VsZCBiZSBpbnZhbGlkLgo+ID4gPgo+ID4g PiBTaWduZWQtb2ZmLWJ5OiBHdW8gUmVuIDxndW9yZW5AbGludXguYWxpYmFiYS5jb20+Cj4gPiA+ IENjOiBBbnVwIFBhdGVsIDxhbnVwQGJyYWluZmF1bHQub3JnPgo+ID4gPiBDYzogVGhvbWFzIEds ZWl4bmVyIDx0Z2x4QGxpbnV0cm9uaXguZGU+Cj4gPiA+IENjOiBNYXJjIFp5bmdpZXIgPG1hekBr ZXJuZWwub3JnPgo+ID4gPiBDYzogUGFsbWVyIERhYmJlbHQgPHBhbG1lckBkYWJiZWx0LmNvbT4K PiA+ID4gQ2M6IEF0aXNoIFBhdHJhIDxhdGlzaC5wYXRyYUB3ZGMuY29tPgo+ID4gPgo+ID4gPiAt LS0KPiA+ID4KPiA+ID4gQ2hhbmdlcyBzaW5jZSBWMjoKPiA+ID4gIC0gQWRkIGEgc2VwYXJhdGUg Y29tcGF0aWJsZSBzdHJpbmcgInRoZWFkLGM5eHgtcGxpYyIKPiA+ID4gIC0gc2V0IGlycV9tYXNr L3VubWFzayBvZiAicGxpY19jaGlwIiB0byBOVUxMIGFuZCBwb2ludAo+ID4gPiAgICBpcnFfZW5h YmxlL2Rpc2FibGUgb2YgInBsaWNfY2hpcCIgdG8gcGxpY19pcnFfbWFzay91bm1hc2sKPiA+ID4g IC0gQWRkIGEgZGV0YWlsZWQgY29tbWVudCBibG9jayBpbiBwbGljX2luaXQoKSBhYm91dCB0aGUK PiA+ID4gICAgZGlmZmVyZW5jZXMgaW4gQ2xhaW0vQ29tcGxldGlvbiBwcm9jZXNzIG9mIFJJU0Mt ViBQTElDIGFuZCBDOXh4Cj4gPiA+ICAgIFBMSUMuCj4gPiA+IC0tLQo+ID4gPiAgZHJpdmVycy9p cnFjaGlwL2lycS1zaWZpdmUtcGxpYy5jIHwgMTcgKysrKysrKysrKysrKysrKysKPiA+ID4gIDEg ZmlsZSBjaGFuZ2VkLCAxNyBpbnNlcnRpb25zKCspCj4gPiA+Cj4gPiA+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2lycWNoaXAvaXJxLXNpZml2ZS1wbGljLmMgYi9kcml2ZXJzL2lycWNoaXAvaXJxLXNp Zml2ZS1wbGljLmMKPiA+ID4gaW5kZXggY2Y3NGNmYTgyMDQ1Li4zNzU2YjFjMTQ3YzMgMTAwNjQ0 Cj4gPiA+IC0tLSBhL2RyaXZlcnMvaXJxY2hpcC9pcnEtc2lmaXZlLXBsaWMuYwo+ID4gPiArKysg Yi9kcml2ZXJzL2lycWNoaXAvaXJxLXNpZml2ZS1wbGljLmMKPiA+ID4gQEAgLTc5LDYgKzc5LDcg QEAgc3RydWN0IHBsaWNfaGFuZGxlciB7Cj4gPiA+ICB9Owo+ID4gPiAgc3RhdGljIGludCBwbGlj X3BhcmVudF9pcnEgX19yb19hZnRlcl9pbml0Owo+ID4gPiAgc3RhdGljIGJvb2wgcGxpY19jcHVo cF9zZXR1cF9kb25lIF9fcm9fYWZ0ZXJfaW5pdDsKPiA+ID4gK3N0YXRpYyBib29sIGRpc2FibGVf bWFza191bm1hc2sgX19yb19hZnRlcl9pbml0Owo+ID4gPiAgc3RhdGljIERFRklORV9QRVJfQ1BV KHN0cnVjdCBwbGljX2hhbmRsZXIsIHBsaWNfaGFuZGxlcnMpOwo+ID4gPgo+ID4gPiAgc3RhdGlj IGlubGluZSB2b2lkIHBsaWNfdG9nZ2xlKHN0cnVjdCBwbGljX2hhbmRsZXIgKmhhbmRsZXIsCj4g PiA+IEBAIC0xODEsNiArMTgyLDEzIEBAIHN0YXRpYyBpbnQgcGxpY19pcnFkb21haW5fbWFwKHN0 cnVjdCBpcnFfZG9tYWluICpkLCB1bnNpZ25lZCBpbnQgaXJxLAo+ID4gPiAgewo+ID4gPiAgICAg ICAgIHN0cnVjdCBwbGljX3ByaXYgKnByaXYgPSBkLT5ob3N0X2RhdGE7Cj4gPiA+Cj4gPiA+ICsg ICAgICAgaWYgKGRpc2FibGVfbWFza191bm1hc2spIHsKPiA+ID4gKyAgICAgICAgICAgICAgIHBs aWNfY2hpcC5pcnFfbWFzayAgICAgID0gTlVMTDsKPiA+ID4gKyAgICAgICAgICAgICAgIHBsaWNf Y2hpcC5pcnFfdW5tYXNrICAgID0gTlVMTDsKPiA+ID4gKyAgICAgICAgICAgICAgIHBsaWNfY2hp cC5pcnFfZW5hYmxlICAgID0gcGxpY19pcnFfdW5tYXNrOwo+ID4gPiArICAgICAgICAgICAgICAg cGxpY19jaGlwLmlycV9kaXNhYmxlICAgPSBwbGljX2lycV9tYXNrOwo+ID4gPiArICAgICAgIH0K PiA+ID4gKwo+ID4gPiAgICAgICAgIGlycV9kb21haW5fc2V0X2luZm8oZCwgaXJxLCBod2lycSwg JnBsaWNfY2hpcCwgZC0+aG9zdF9kYXRhLAo+ID4gPiAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgaGFuZGxlX2Zhc3Rlb2lfaXJxLCBOVUxMLCBOVUxMKTsKPiA+ID4gICAgICAgICBpcnFfc2V0 X25vcHJvYmUoaXJxKTsKPiA+ID4gQEAgLTM5MCw1ICszOTgsMTQgQEAgc3RhdGljIGludCBfX2lu aXQgcGxpY19pbml0KHN0cnVjdCBkZXZpY2Vfbm9kZSAqbm9kZSwKPiA+ID4gICAgICAgICByZXR1 cm4gZXJyb3I7Cj4gPiA+ICB9Cj4gPiA+Cj4gPiA+ICtzdGF0aWMgaW50IF9faW5pdCB0aGVhZF9j OXh4X3BsaWNfaW5pdChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5vZGUsCj4gPiA+ICsgICAgICAgICAg ICAgICBzdHJ1Y3QgZGV2aWNlX25vZGUgKnBhcmVudCkKPiA+ID4gK3sKPiA+ID4gKyAgICAgICBk aXNhYmxlX21hc2tfdW5tYXNrID0gdHJ1ZTsKPiA+Cj4gPiBUaGUgcGxpY19pcnFkb21haW5fbWFw KCkgaXMgY2FsbGVkIGZvciBlYWNoIGlycSBzbyAicGxpY19jaGlwIgo+ID4gd2lsbCBiZSB1cGRh dGVkIG11bHRpcGxlIHRpbWVzLgo+ID4KPiA+IFlvdSBjYW4gZHJvcCB0aGUgZGlzYWJsZV9tYXNr X3VubWFzayB2YXJpYWJsZSBhbmQgaW5zdGVhZAo+ID4gZGlyZWN0bHkgdXBkYXRlICJwbGljX2No aXAiIGhlcmUuCj4KPiBBY3R1YWxseSBJJ2QgdGhpbmsgc29tZXRoaW5nIG1vcmUgZHluYW1pYyBt aWdodCBiZSBhcHByb3ByaWF0ZT8KPgo+IEkuZS4gZG9uJ3QgbW9kaWZ5IHRoZSBnZW5lcmljIHBs aWNfY2hpcCBzdHJ1Y3R1cmUsIGJ1dCBkZWZpbmUgYSBzZWNvbmQKPiBvbmUgZm9yIHRoaXMgdHlw ZSBvZiBjaGlwIGFuZCByZWZlcmVuY2UgdGhhdCBvbmUgaW4gcGxpY19pcnFkb21haW5fbWFwCj4g ZGVwZW5kaW5nIG9uIHRoZSBibG9jayBmb3VuZD8KPgo+IEFjY29yZGluZyB0byBbMF0gYSBzeXN0 ZW0gY2FuIGhhdmUgbXVsdGlwbGUgUExJQ3MgYW5kIG5vdGhpbmcKPiBndWFyYW50ZWVzIHRoYXQg dGhleSdsbCBhbHdheXMgYmUgdGhlIHNhbWUgdmFyaWFudCBvbiBmdXR1cmUgc29jcwo+IFtoYXJk d2FyZSBlbmdpbmVlcnMgYXJlIHZlcnkgY3JlYXRpdmVdCj4KPiBTbyBhZGRpbmcgbW9yZSBzdHVm ZiB0aGF0IG1vZGlmaWVzIHN0YXRpYyBjb250ZW50IHVzZWQgYnkgYWxsIFBMSUNzCj4gZG9lc24n dCByZWFsbHkgaW1wcm92ZSBkcml2ZXIgcXVhbGl0eSBoZXJlIDstKQpBZ3JlZSwgSSBsaWtlIHlv dXIgc3R5bGUgYmVjYXVzZSBpdCBhbHNvIGNvdWxkIG1ha2UgY2F0Ci9wcm9jL2ludGVycnVwdHMg bmFtZSBwcm9wZXJseS4KCnN0YXRpYyBzdHJ1Y3QgaXJxX2NoaXAgc2lmaXZlX3BsaWNfY2hpcCA9 IHsKICAgICAgICAubmFtZSAgICAgICAgICAgPSAiU2lGaXZlIFBMSUMiLAoKc3RhdGljIHN0cnVj dCBpcnFfY2hpcCB0aGVhZF9wbGljX2NoaXAgPSB7CiAgICAgICAgLm5hbWUgICAgICAgICAgID0g IlQtSEVBRCBQTElDIiwKPgo+Cj4gSGVpa28KPgo+Cj4gWzBdIGh0dHBzOi8vbG9yZS5rZXJuZWwu b3JnL2xpbnV4LXJpc2N2LzE4MzliZjllZjkxZGUyMzU4YTdlOGVjYWRlMzYxZjdhQHd3dy5sb2Vu LmZyL1QvCj4KPgo+ID4KPiA+ID4gKwo+ID4gPiArICAgICAgIHJldHVybiBwbGljX2luaXQobm9k ZSwgcGFyZW50KTsKPiA+ID4gK30KPiA+ID4gKwo+ID4gPiAgSVJRQ0hJUF9ERUNMQVJFKHNpZml2 ZV9wbGljLCAic2lmaXZlLHBsaWMtMS4wLjAiLCBwbGljX2luaXQpOwo+ID4gPiAgSVJRQ0hJUF9E RUNMQVJFKHJpc2N2X3BsaWMwLCAicmlzY3YscGxpYzAiLCBwbGljX2luaXQpOyAvKiBmb3IgbGVn YWN5IHN5c3RlbXMgKi8KPiA+ID4gK0lSUUNISVBfREVDTEFSRSh0aGVhZF9jOXh4X3BsaWMsICJ0 aGVhZCxjOXh4LXBsaWMiLCB0aGVhZF9jOXh4X3BsaWNfaW5pdCk7Cj4gPiA+IC0tCj4gPiA+IDIu MjUuMQo+ID4gPgo+ID4KPiA+IFJlZ2FyZHMsCj4gPiBBbnVwCj4gPgo+ID4gX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KPiA+IGxpbnV4LXJpc2N2IG1haWxp bmcgbGlzdAo+ID4gbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwo+ID4gaHR0cDovL2xp c3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yaXNjdgo+ID4KPgo+Cj4K PgoKCi0tIApCZXN0IFJlZ2FyZHMKIEd1byBSZW4KCk1MOiBodHRwczovL2xvcmUua2VybmVsLm9y Zy9saW51eC1jc2t5LwoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVh ZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1y aXNjdgo=