From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77691C433EF for ; Wed, 29 Jun 2022 08:24:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231219AbiF2IYV (ORCPT ); Wed, 29 Jun 2022 04:24:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231811AbiF2IYT (ORCPT ); Wed, 29 Jun 2022 04:24:19 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E9533BBFB; Wed, 29 Jun 2022 01:24:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 3B6E5B8213E; Wed, 29 Jun 2022 08:24:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B9C7C341CD; Wed, 29 Jun 2022 08:24:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656491056; bh=Pd/spSg+y88wI0co/eA7QGJBokO/5IsoxHQjfzfNeNQ=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=SO6r41zu5WHMzyprs15T8STTIn1h61qoaP6FWzWM7MI+nHRgMR72CY6Rnfo7T6+H9 dpG47nKcdqumO2iOKZPUwv7rNugQ9GA24SMp3ZmL1VG+UrwRIMM2oU4IxYjhIBbZFZ a2uYU8/jIopWKJN/+93ubw97TxMgGJM9dX3HJqA9YMcZXxgLba7DTuHt7YfqrxUAi5 sWnCjZG7C/yGWXyquaHs8TjsWm8DyhkmCKBw+kHRj8afWwZFF35di58yC/edyFhV0S nAUHwMe/l0BBVHnHAmq4ecoGz4snrqX3nckBuyFQXgXe+rcdMVZQy7Z6y0WtVixyO0 /RzkvCZEr/HXg== Received: by mail-ua1-f52.google.com with SMTP id p19so5466667uam.4; Wed, 29 Jun 2022 01:24:15 -0700 (PDT) X-Gm-Message-State: AJIora/8v+v0JZe+rBbtJiGHuiQs0X2FriX1Tog6XxylP4IYrMEoKHMw nGXntFIDfsBBEdO69POpwLJ36PGZ437GhFmId6s= X-Google-Smtp-Source: AGRyM1s0lSpAvkZFNGtXOSIIAgmco0eMrVwqMgEgvH2vWSidbf8ha7cbiRkvf3Y/sQ9onF8WNaDUfMl/uj71l3N1hZE= X-Received: by 2002:a9f:23c2:0:b0:365:958:e807 with SMTP id 60-20020a9f23c2000000b003650958e807mr598894uao.114.1656491054985; Wed, 29 Jun 2022 01:24:14 -0700 (PDT) MIME-Version: 1.0 References: <20220628081707.1997728-1-guoren@kernel.org> <20220628081707.1997728-5-guoren@kernel.org> <09abc75e-2ffb-1ab5-d0fc-1c15c943948d@redhat.com> <5166750c-3dc6-9b09-4a1e-cd53141cdde8@redhat.com> In-Reply-To: From: Guo Ren Date: Wed, 29 Jun 2022 16:24:03 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V7 4/5] asm-generic: spinlock: Add combo spinlock (ticket & queued) To: Arnd Bergmann Cc: Waiman Long , Palmer Dabbelt , Ingo Molnar , Will Deacon , Boqun Feng , linux-riscv , linux-arch , Linux Kernel Mailing List , Guo Ren , Peter Zijlstra Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 29, 2022 at 3:09 PM Arnd Bergmann wrote: > > On Wed, Jun 29, 2022 at 3:34 AM Waiman Long wrote: > > On 6/28/22 21:17, Guo Ren wrote: > > > On Wed, Jun 29, 2022 at 2:13 AM Waiman Long wrote: > > >> On 6/28/22 04:17, guoren@kernel.org wrote: > > >> > > >> So the current config setting determines if qspinlock will be used, not > > >> some boot time parameter that user needs to specify. This patch will > > >> just add useless code to lock/unlock sites. I don't see any benefit of > > >> doing that. > > > This is a startup patch for riscv. next, we could let vendors make choices. > > > I'm not sure they like cmdline or vendor-specific errata style. > > > > > > Eventually, we would let one riscv Image support all machines, some > > > use ticket-lock, and some use qspinlock. > > > > OK. Maybe you can postpone this combo spinlock until there is a good use > > case for it. Upstream usually don't accept patches that have no good use > > case yet. > > I think the usecase on risc-v is this: there are cases where the qspinlock > is preferred for performance reasons, but there are also CPU cores on > which it is not safe to use. risc-v like most modern architectures has a > strict rule about being able to build kernels that work on all machines, > so without something like this, it would not be able to use qspinlock at all. > > On the other hand, I don't really like the idea of putting the static-key > wrapper into the asm-generic header. Especially the ticket spinlock > implementation should be simple and not depend on jump labels. If CONFIG_ARCH_USE_QUEUED_SPINLOCKS is not enabled, the patch still will keep the ticket-lock simple without jump labels. > > From looking at the header file dependencies on arm64, I know that > putting jump labels into core infrastructure like the arch_spin_lock() > makes a big mess of indirect includes and measurably slows down > the kernel build. arm64 needn't combo spinlock, it could use pure qspinlock with keeping current header files included. > > I think this can still be done in the riscv asm/spinlock.h header with > minimal impact on the asm-generic file if the riscv maintainers see > a significant enough advantage, but I don't want it in the common code. Yes, it could. I agree with using combo spinlock only with riscv. > > Arnd -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19407C43334 for ; Wed, 29 Jun 2022 08:24:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8FUslt7sjKaCp5pS8zQUbTjET91o4C4doyX/uN+RFWo=; b=0D7joxtB1pAZtV T+ZHYGqJYRpuh2fZ64ytm0YQ44dmLo9I7PIamGYYF7GS25ArXusdWGShkv7wG9b65yQO4EdCYivCF OiR1eFEvT1vkixmbsozQLVp/C5YuvTB3Gi4iTSBC9QD50Z+u8p03KWN6tJS7cZVo9T2QkvlLMXxw4 rznMpN6h8AEzJNm5zBAO3qJKsFRQMTTmUjQ3r/i6qeyLqzVNxRUyfWQ0J3o2PItu/z1/aGnUsRfwg 5s64WtGC7nqI/rwpJyLlwC7L1J5HtHTA/sX74cSh9IICc/txGSkQcdoCyMjnucxUdVJzy6eW/a/3r usU0L6rAPwZfC8flFI5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6Szr-00ANBx-1d; Wed, 29 Jun 2022 08:24:27 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6Szi-00AN5a-Ey for linux-riscv@lists.infradead.org; Wed, 29 Jun 2022 08:24:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 30FFA61D68 for ; Wed, 29 Jun 2022 08:24:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 10233C341CC for ; Wed, 29 Jun 2022 08:24:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656491056; bh=Pd/spSg+y88wI0co/eA7QGJBokO/5IsoxHQjfzfNeNQ=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=SO6r41zu5WHMzyprs15T8STTIn1h61qoaP6FWzWM7MI+nHRgMR72CY6Rnfo7T6+H9 dpG47nKcdqumO2iOKZPUwv7rNugQ9GA24SMp3ZmL1VG+UrwRIMM2oU4IxYjhIBbZFZ a2uYU8/jIopWKJN/+93ubw97TxMgGJM9dX3HJqA9YMcZXxgLba7DTuHt7YfqrxUAi5 sWnCjZG7C/yGWXyquaHs8TjsWm8DyhkmCKBw+kHRj8afWwZFF35di58yC/edyFhV0S nAUHwMe/l0BBVHnHAmq4ecoGz4snrqX3nckBuyFQXgXe+rcdMVZQy7Z6y0WtVixyO0 /RzkvCZEr/HXg== Received: by mail-ua1-f51.google.com with SMTP id l27so154949uac.10 for ; Wed, 29 Jun 2022 01:24:15 -0700 (PDT) X-Gm-Message-State: AJIora9q/nuBnmu2rJTss23pZYZzzV/+0TUZ0V0MDFUS6wk796TPVbax 5wf4lDHFRF4f995BZijcVKVNuQzSbO4PdJ/GrZg= X-Google-Smtp-Source: AGRyM1s0lSpAvkZFNGtXOSIIAgmco0eMrVwqMgEgvH2vWSidbf8ha7cbiRkvf3Y/sQ9onF8WNaDUfMl/uj71l3N1hZE= X-Received: by 2002:a9f:23c2:0:b0:365:958:e807 with SMTP id 60-20020a9f23c2000000b003650958e807mr598894uao.114.1656491054985; Wed, 29 Jun 2022 01:24:14 -0700 (PDT) MIME-Version: 1.0 References: <20220628081707.1997728-1-guoren@kernel.org> <20220628081707.1997728-5-guoren@kernel.org> <09abc75e-2ffb-1ab5-d0fc-1c15c943948d@redhat.com> <5166750c-3dc6-9b09-4a1e-cd53141cdde8@redhat.com> In-Reply-To: From: Guo Ren Date: Wed, 29 Jun 2022 16:24:03 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V7 4/5] asm-generic: spinlock: Add combo spinlock (ticket & queued) To: Arnd Bergmann Cc: Waiman Long , Palmer Dabbelt , Ingo Molnar , Will Deacon , Boqun Feng , linux-riscv , linux-arch , Linux Kernel Mailing List , Guo Ren , Peter Zijlstra X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220629_012418_642274_BDF7F80E X-CRM114-Status: GOOD ( 35.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Jun 29, 2022 at 3:09 PM Arnd Bergmann wrote: > > On Wed, Jun 29, 2022 at 3:34 AM Waiman Long wrote: > > On 6/28/22 21:17, Guo Ren wrote: > > > On Wed, Jun 29, 2022 at 2:13 AM Waiman Long wrote: > > >> On 6/28/22 04:17, guoren@kernel.org wrote: > > >> > > >> So the current config setting determines if qspinlock will be used, not > > >> some boot time parameter that user needs to specify. This patch will > > >> just add useless code to lock/unlock sites. I don't see any benefit of > > >> doing that. > > > This is a startup patch for riscv. next, we could let vendors make choices. > > > I'm not sure they like cmdline or vendor-specific errata style. > > > > > > Eventually, we would let one riscv Image support all machines, some > > > use ticket-lock, and some use qspinlock. > > > > OK. Maybe you can postpone this combo spinlock until there is a good use > > case for it. Upstream usually don't accept patches that have no good use > > case yet. > > I think the usecase on risc-v is this: there are cases where the qspinlock > is preferred for performance reasons, but there are also CPU cores on > which it is not safe to use. risc-v like most modern architectures has a > strict rule about being able to build kernels that work on all machines, > so without something like this, it would not be able to use qspinlock at all. > > On the other hand, I don't really like the idea of putting the static-key > wrapper into the asm-generic header. Especially the ticket spinlock > implementation should be simple and not depend on jump labels. If CONFIG_ARCH_USE_QUEUED_SPINLOCKS is not enabled, the patch still will keep the ticket-lock simple without jump labels. > > From looking at the header file dependencies on arm64, I know that > putting jump labels into core infrastructure like the arch_spin_lock() > makes a big mess of indirect includes and measurably slows down > the kernel build. arm64 needn't combo spinlock, it could use pure qspinlock with keeping current header files included. > > I think this can still be done in the riscv asm/spinlock.h header with > minimal impact on the asm-generic file if the riscv maintainers see > a significant enough advantage, but I don't want it in the common code. Yes, it could. I agree with using combo spinlock only with riscv. > > Arnd -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv