From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CBEDC433E0 for ; Wed, 24 Mar 2021 12:11:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B33AB61A05 for ; Wed, 24 Mar 2021 12:11:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233153AbhCXMLU (ORCPT ); Wed, 24 Mar 2021 08:11:20 -0400 Received: from mail.kernel.org ([198.145.29.99]:59610 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233100AbhCXMLL (ORCPT ); Wed, 24 Mar 2021 08:11:11 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E044261A0A for ; Wed, 24 Mar 2021 12:11:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616587863; bh=kEx0TIsJHajLeIyFUwPJAU5kpomMAoLZGOL83edNDYM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=AnSjMG9UhEB4+85PdfpildgQIi/Yq58nviKe6bZkBkVeXl/4OMOhzilxaoK5MqKhJ kvzWlpvlIhUG8JNvkVzUlU3g5UiUl4btFKKJiYg/bu6cbuwUKghX7vwudnOj6P8Gk7 rvlXPJy761kqBC76BhZ1+wLV/y750e8e5CBV0edSKzqi95C9xNv1PQ5QD4jbr9z3gy TMa7jNLIC+mqs+qlQ4BmkdO8+W5ngc5X80y9f3G18/1FLsnF5BEn2ErmUjU+A9G9Ka N7GHZZATIKFxcGEE8QhEoZBYr2Nyt3w8Dpo/xdR7Unksp79H7KYOMxtiOvvxdoSdRV Tr1FshV3f1I4g== Received: by mail-lj1-f175.google.com with SMTP id z8so29847257ljm.12 for ; Wed, 24 Mar 2021 05:11:02 -0700 (PDT) X-Gm-Message-State: AOAM530/vydhLGAGd/SqXRSSD7GUV3IZS6XXJAyYlmipXUdEO1Eg2deu onBizf4SWkOqr76kOQrWO8M1qUm002SHSoPQqO8= X-Google-Smtp-Source: ABdhPJzViXtP8zyzgXEgbL2g8vAs/9lwuvKdvQdVrCRF9Rz67/eCIn1+cEAu3zCO2mhfx2EctG6Feq95zSC122HKV9w= X-Received: by 2002:a2e:994e:: with SMTP id r14mr1940414ljj.115.1616587861091; Wed, 24 Mar 2021 05:11:01 -0700 (PDT) MIME-Version: 1.0 References: <1616580892-80815-1-git-send-email-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Wed, 24 Mar 2021 20:10:49 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation To: Peter Zijlstra Cc: linux-riscv , Linux Kernel Mailing List , Guo Ren , Catalin Marinas , Will Deacon , Palmer Dabbelt , Anup Patel , Arnd Bergmann Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thx Peter, On Wed, Mar 24, 2021 at 7:09 PM Peter Zijlstra wrote: > > On Wed, Mar 24, 2021 at 10:14:52AM +0000, guoren@kernel.org wrote: > > +static inline void arch_spin_lock(arch_spinlock_t *lock) > > +{ > > + arch_spinlock_t lockval; > > + u32 tmp; > > + > > + asm volatile ( > > + "1: lr.w %0, %2 \n" > > + " mv %1, %0 \n" > > + " addw %0, %0, %3 \n" > > + " sc.w %0, %0, %2 \n" > > + " bnez %0, 1b \n" > > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT) > > + : "memory"); > > > > + while (lockval.tickets.next != lockval.tickets.owner) { > > + /* > > + * FIXME - we need wfi/wfe here to prevent: > > + * - cache line bouncing > > + * - saving cpu pipeline in multi-harts-per-core > > + * processor > > + */ > > + lockval.tickets.owner = READ_ONCE(lock->tickets.owner); > > + } > > > > + __atomic_acquire_fence(); > > } > > > +static inline void arch_spin_unlock(arch_spinlock_t *lock) > > { > > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1); > > + /* FIXME - we need ipi/sev here to notify above */ > > } > > Urgh, are you saying your WFE requires an explicit SEV like on ARM ? The Yes, I'm considering that kind of code. > ARM64 model is far superious IMO, and then you can use > smp_cond_load_acquire() in arch_spin_lock() and call it a day. Great tip, thx. I'll follow that. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3438C433DB for ; Wed, 24 Mar 2021 12:11:31 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 765F461A02 for ; Wed, 24 Mar 2021 12:11:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 765F461A02 Authentication-Results: mail.kernel.org; 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Wed, 24 Mar 2021 05:11:02 -0700 (PDT) X-Gm-Message-State: AOAM531BFASoEEzV8s6O35+ow8ZUFllKbM0giCVCeQejsCQYG17uFsoi mPvsyax/jUpaOAGGAS5FVlVk8i/u/oUhbqXIn8A= X-Google-Smtp-Source: ABdhPJzViXtP8zyzgXEgbL2g8vAs/9lwuvKdvQdVrCRF9Rz67/eCIn1+cEAu3zCO2mhfx2EctG6Feq95zSC122HKV9w= X-Received: by 2002:a2e:994e:: with SMTP id r14mr1940414ljj.115.1616587861091; Wed, 24 Mar 2021 05:11:01 -0700 (PDT) MIME-Version: 1.0 References: <1616580892-80815-1-git-send-email-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Wed, 24 Mar 2021 20:10:49 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation To: Peter Zijlstra Cc: linux-riscv , Linux Kernel Mailing List , Guo Ren , Catalin Marinas , Will Deacon , Palmer Dabbelt , Anup Patel , Arnd Bergmann X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210324_121110_679545_F4A0294D X-CRM114-Status: GOOD ( 12.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Thx Peter, On Wed, Mar 24, 2021 at 7:09 PM Peter Zijlstra wrote: > > On Wed, Mar 24, 2021 at 10:14:52AM +0000, guoren@kernel.org wrote: > > +static inline void arch_spin_lock(arch_spinlock_t *lock) > > +{ > > + arch_spinlock_t lockval; > > + u32 tmp; > > + > > + asm volatile ( > > + "1: lr.w %0, %2 \n" > > + " mv %1, %0 \n" > > + " addw %0, %0, %3 \n" > > + " sc.w %0, %0, %2 \n" > > + " bnez %0, 1b \n" > > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT) > > + : "memory"); > > > > + while (lockval.tickets.next != lockval.tickets.owner) { > > + /* > > + * FIXME - we need wfi/wfe here to prevent: > > + * - cache line bouncing > > + * - saving cpu pipeline in multi-harts-per-core > > + * processor > > + */ > > + lockval.tickets.owner = READ_ONCE(lock->tickets.owner); > > + } > > > > + __atomic_acquire_fence(); > > } > > > +static inline void arch_spin_unlock(arch_spinlock_t *lock) > > { > > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1); > > + /* FIXME - we need ipi/sev here to notify above */ > > } > > Urgh, are you saying your WFE requires an explicit SEV like on ARM ? The Yes, I'm considering that kind of code. > ARM64 model is far superious IMO, and then you can use > smp_cond_load_acquire() in arch_spin_lock() and call it a day. Great tip, thx. I'll follow that. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv