Re: [dpdk-dev] [PATCH] ci: fix aarch64 cross compilation in GHA

[David Marchand <david.marchand@redhat.com>]

On Fri, Oct 29, 2021 at 11:26 AM David Marchand
<david.marchand@redhat.com> wrote:
>
> Afaics, CC_FOR_BUILD is a Travis env variable.
> This results in GHA aarch64 cross compilation jobs building x86
> binaries.
>
> Example in a recent job on main branch:
> 2021-10-28T09:51:06.4976495Z + .ci/linux-build.sh
> 2021-10-28T09:51:06.4985674Z + [ -n build ]
> 2021-10-28T09:51:06.4987636Z + [ true = true ]
> 2021-10-28T09:51:06.4987991Z + [  = gcc ]
> 2021-10-28T09:51:06.4989419Z + [  = clang ]
> 2021-10-28T09:51:06.4990907Z + [ false = true ]
> 2021-10-28T09:51:06.4991348Z + [ false = true ]
> 2021-10-28T09:51:06.4992846Z + [ static = static ]
> 2021-10-28T09:51:06.4993550Z + OPTS= -Dexamples=l2fwd,l3fwd
> 2021-10-28T09:51:06.4995388Z + OPTS= -Dexamples=l2fwd,l3fwd
> -Dplatform=generic
> 2021-10-28T09:51:06.4996279Z + OPTS= -Dexamples=l2fwd,l3fwd
> -Dplatform=generic --default-library=static
> 2021-10-28T09:51:06.4998553Z + OPTS= -Dexamples=l2fwd,l3fwd
> -Dplatform=generic --default-library=static --buildtype=debugoptimized
> 2021-10-28T09:51:06.4999949Z + OPTS= -Dexamples=l2fwd,l3fwd
> -Dplatform=generic --default-library=static --buildtype=debugoptimized
> -Dcheck_includes=true
> 2021-10-28T09:51:06.5002643Z + meson build --werror
> -Dexamples=l2fwd,l3fwd -Dplatform=generic --default-library=static
> --buildtype=debugoptimized -Dcheck_includes=true
>
> Fixes: 5d0b4ffa6964 ("ci: add aarch64 clang cross-compilation Travis builds")
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>
> ---
> This patch can't be merged right away, since build issues are now raised
> in GHA.
> Please ARM people, have a look.
> Thanks.

https://github.com/ovsrobot/dpdk/runs/4045007618?check_suite_focus=true

[2123/2985] Compiling C object
'drivers/a715181@@tmp_rte_event_cnxk@sta/event_cnxk_cn10k_worker_deq_ca.c.o'.
FAILED: drivers/a715181@@tmp_rte_event_cnxk@sta/event_cnxk_cn10k_worker_deq_ca.c.o
aarch64-linux-gnu-gcc -Idrivers/a715181@@tmp_rte_event_cnxk@sta
-Idrivers -I../drivers -Idrivers/event/cnxk -I../drivers/event/cnxk
-Ilib/eventdev -I../lib/eventdev -I. -I../ -Iconfig -I../config
-Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include
-I../lib/eal/linux/include -Ilib/eal/arm/include
-I../lib/eal/arm/include -Ilib/eal/common -I../lib/eal/common
-Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs
-Ilib/telemetry/../metrics -I../lib/telemetry/../metrics
-Ilib/telemetry -I../lib/telemetry -Ilib/ring -I../lib/ring
-Ilib/ethdev -I../lib/ethdev -Ilib/net -I../lib/net -Ilib/mbuf
-I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/meter
-I../lib/meter -Ilib/hash -I../lib/hash -Ilib/rcu -I../lib/rcu
-Ilib/timer -I../lib/timer -Ilib/cryptodev -I../lib/cryptodev
-Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
-Ilib/pci -I../lib/pci -Idrivers/common/cnxk -I../drivers/common/cnxk
-Idrivers/common/cnxk/../../bus/pci
-I../drivers/common/cnxk/../../bus/pci
-Idrivers/common/cnxk/../../../lib/net
-I../drivers/common/cnxk/../../../lib/net
-Idrivers/common/cnxk/../../../lib/ethdev
-I../drivers/common/cnxk/../../../lib/ethdev
-Idrivers/common/cnxk/../../../lib/meter
-I../drivers/common/cnxk/../../../lib/meter -Ilib/security
-I../lib/security -Idrivers/net/cnxk -I../drivers/net/cnxk
-Idrivers/bus/vdev -I../drivers/bus/vdev -Idrivers/mempool/cnxk
-I../drivers/mempool/cnxk -Idrivers/crypto/cnxk
-I../drivers/crypto/cnxk -Idrivers/crypto/cnxk/../../../lib/net
-I../drivers/crypto/cnxk/../../../lib/net -fdiagnostics-color=always
-pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O2 -g
-include rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat
-Wformat-nonliteral -Wformat-security -Wmissing-declarations
-Wmissing-prototypes -Wnested-externs -Wold-style-definition
-Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef
-Wwrite-strings -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC
-march=armv8-a+crc -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API
-Wno-format-truncation -flax-vector-conversions -Wno-strict-aliasing
-DRTE_LOG_DEFAULT_LOGTYPE=pmd.event.cnxk -MD -MQ
'drivers/a715181@@tmp_rte_event_cnxk@sta/event_cnxk_cn10k_worker_deq_ca.c.o'
-MF 'drivers/a715181@@tmp_rte_event_cnxk@sta/event_cnxk_cn10k_worker_deq_ca.c.o.d'
-o 'drivers/a715181@@tmp_rte_event_cnxk@sta/event_cnxk_cn10k_worker_deq_ca.c.o'
-c ../drivers/event/cnxk/cn10k_worker_deq_ca.c
{standard input}: Assembler messages:
{standard input}:799: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:3314: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:11923: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:14807: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:16771: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:17883: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x5]'
{standard input}:20012: Error: reg pair must start from even reg at
operand 1 -- `caspl x11,x12,x11,x12,[x4]'
{standard input}:21194: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x5]'
{standard input}:24342: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:27403: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:45147: Error: reg pair must start from even reg at
operand 1 -- `caspl x15,x16,x15,x16,[x5]'
{standard input}:49266: Error: reg pair must start from even reg at
operand 1 -- `caspl x15,x16,x15,x16,[x5]'
{standard input}:56283: Error: reg pair must start from even reg at
operand 1 -- `caspl x15,x16,x15,x16,[x4]'
{standard input}:58457: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:59932: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:62327: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:63856: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:66288: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:69922: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:75289: Error: reg pair must start from even reg at
operand 1 -- `caspl x17,x18,x17,x18,[x5]'
{standard input}:83560: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:87393: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:89816: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:94130: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:98635: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:100325: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:102889: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:104626: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:107220: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x2]'
{standard input}:112059: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x2]'
{standard input}:117986: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x4]'
{standard input}:121023: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x4]'
{standard input}:131204: Error: reg pair must start from even reg at
operand 1 -- `caspl x17,x18,x17,x18,[x4]'
{standard input}:133441: Error: reg pair must start from even reg at
operand 1 -- `caspl x7,x8,x7,x8,[x4]'
{standard input}:134751: Error: reg pair must start from even reg at
operand 1 -- `caspl x17,x18,x17,x18,[x4]'
{standard input}:137052: Error: reg pair must start from even reg at
operand 1 -- `caspl x7,x8,x7,x8,[x4]'
{standard input}:138528: Error: reg pair must start from even reg at
operand 1 -- `caspl x15,x16,x15,x16,[x5]'
{standard input}:141011: Error: reg pair must start from even reg at
operand 1 -- `caspl x7,x8,x7,x8,[x4]'
{standard input}:142549: Error: reg pair must start from even reg at
operand 1 -- `caspl x15,x16,x15,x16,[x5]'
{standard input}:149947: Error: reg pair must start from even reg at
operand 1 -- `caspl x17,x18,x17,x18,[x4]'
{standard input}:153785: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x5]'
{standard input}:157805: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x5]'
{standard input}:168528: Error: reg pair must start from even reg at
operand 1 -- `caspl x7,x8,x7,x8,[x3]'
{standard input}:182834: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:185239: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:189542: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:193925: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:195587: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:198151: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x4]'
{standard input}:199857: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x4]'
{standard input}:202475: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x2]'
{standard input}:207339: Error: reg pair must start from even reg at
operand 1 -- `caspl x9,x10,x9,x10,[x2]'
{standard input}:218197: Error: reg pair must start from even reg at
operand 1 -- `caspl x23,x24,x23,x24,[x4]'
{standard input}:256955: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x4]'
{standard input}:258753: Error: reg pair must start from even reg at
operand 1 -- `caspl x23,x24,x23,x24,[x0]'
{standard input}:264566: Error: reg pair must start from even reg at
operand 1 -- `caspl x23,x24,x23,x24,[x0]'
{standard input}:299615: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x0]'
{standard input}:308393: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:314761: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:333316: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:339849: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:346259: Error: reg pair must start from even reg at
operand 1 -- `caspl x5,x6,x5,x6,[x0]'
{standard input}:352566: Error: reg pair must start from even reg at
operand 1 -- `caspl x3,x4,x3,x4,[x0]'
{standard input}:409947: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:413049: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:417049: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:420238: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:445261: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:452790: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x0]'
{standard input}:470858: Error: reg pair must start from even reg at
operand 1 -- `caspl x25,x26,x25,x26,[x0]'
{standard input}:491830: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:498232: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:558070: Error: reg pair must start from even reg at
operand 1 -- `caspl x3,x4,x3,x4,[x0]'
{standard input}:564810: Error: reg pair must start from even reg at
operand 1 -- `caspl x21,x22,x21,x22,[x0]'
{standard input}:568689: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:571755: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:575701: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:578839: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:603742: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:625583: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:628910: Error: reg pair must start from even reg at
operand 1 -- `caspl x7,x8,x7,x8,[x0]'
{standard input}:633102: Error: reg pair must start from even reg at
operand 1 -- `caspl x27,x28,x27,x28,[x0]'
{standard input}:636505: Error: reg pair must start from even reg at
operand 1 -- `caspl x7,x8,x7,x8,[x0]'
[2124/2985] Compiling C object
'drivers/a715181@@tmp_rte_event_cnxk@sta/event_cnxk_cn10k_worker_tx_enq.c.o'.
ninja: build stopped: subcommand failed.
Error: Process completed with exit code 1.



-- 
David Marchand