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Thu, 28 Jan 2021 00:19:08 -0800 (PST) MIME-Version: 1.0 References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> In-Reply-To: <1611821396.1947.10.camel@mhfsdcap03> From: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:18:42 +0800 Message-ID: Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function To: Yongqiang Niu Cc: CK Hu , Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , dri-devel , Devicetree List , lkml , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/Mediatek SoC support" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > From: Yongqiang Niu > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > to improve the display quality > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > Signed-off-by: Hsin-Yi Wang > > > > > --- > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > index 8173f709272be..e85625704d611 100644 > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > @@ -53,7 +53,9 @@ > > > > > #define DITHER_EN BIT(0) > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > { > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > + bool enable = false; > > > > > + > > > > > + /* default value for dither reg 5 to 14 */ > > > > > + const u32 dither_setting[] = { > > > > > + 0x00000000, /* 5 */ > > > > > + 0x00003002, /* 6 */ > > > > > + 0x00000000, /* 7 */ > > > > > + 0x00000000, /* 8 */ > > > > > + 0x00000000, /* 9 */ > > > > > + 0x00000000, /* 10 */ > > > > > + 0x00000000, /* 11 */ > > > > > + 0x00000011, /* 12 */ > > > > > + 0x00000000, /* 13 */ > > > > > + 0x00000000, /* 14 */ > > > > > > > > Could you explain what is this? > > > > > > this is dither 5 to dither 14 setting > > > this will be useless, we just need set dither 5 and dither 7 like > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > other value is same with hardware default value. > > > > > > > > > > > > > > > + }; > > > > > + > > > > > + if (bpc == 5 || bpc == 6) { > > > > > + enable = true; > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_NEW_BIT_MODE, > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > version is correct and previous version is incorrect? > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > mtk_dither_set() instead of duplication here. > > > > dither enable set in mtk_dither_set is > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > that is different 8183 and mt8192. > mt8173 dither enable in gamma is bit2 > mt8183 and mt8192 dither engine enable is bit 1 > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1. Is this reasonable? > > Regards, > > CK > > > > > > > > Regards, > > > > CK > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > + } > > > > > + > > > > > + > > > > > + if (enable) { > > > > > + u32 idx; > > > > > + > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > + DITHER_REG(idx + 5)); > > > > > + } > > > > > + > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > } > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54443C433E0 for ; Thu, 28 Jan 2021 08:19:27 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E63D96146D for ; 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bh=D7f6UU2qkF6tlfnpAtMyZPF2/NarOHZ3GCaIjhXM6L0=; b=YCxVDk61GqBp6KjEyJ0bIqhFXkTltbzTmWNOLTQTBXD+4cRqVuMrAdktoxJ47e35km dKp2cFcMBkbu6ftanXydZLUwqvgoBKOScQQKlvkTEt7pRaP+MJckjIviknsvvxKNohC5 ai4/fyxfhIIBpJsq096NFioj2KyVJmnG6O0UhikFmpj7z23OC1l+YdWwxtjL9rIbcEgI PANJK7sCefPcWyA3Qv9V2peH1AgtOjR0k0WboaEgWf9CCWDxdgU5s+y5UpnJ3/Gcdit8 9xQflMkDV6DqZcv4YjN9aUDqX0KzzKzTXpjp/xP/Dp3AIf0eNLAKABbzKFNQxYwVtM9u i46Q== X-Gm-Message-State: AOAM532RdYycp9uYMHk/K5f3jL+dmhmtu+9J8E/VL4O4GmyggagJiDND m23YkEoz/s/C77Z0Tfuy0kqFpIF3nRIuK3keE7BxCQ== X-Google-Smtp-Source: ABdhPJy8CohiK7DuY6bT4ie39DRCyEWXlmXddonmwi5vsWuH4gheLsdx40UweC8SKCWBOA6AM66CZddl24p81cDx0hM= X-Received: by 2002:a05:6638:b12:: with SMTP id a18mr12268624jab.114.1611821948718; Thu, 28 Jan 2021 00:19:08 -0800 (PST) MIME-Version: 1.0 References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> In-Reply-To: <1611821396.1947.10.camel@mhfsdcap03> From: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:18:42 +0800 Message-ID: Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function To: Yongqiang Niu X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_031910_768006_EB746EB1 X-CRM114-Status: GOOD ( 30.39 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , CK Hu , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > From: Yongqiang Niu > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > to improve the display quality > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > Signed-off-by: Hsin-Yi Wang > > > > > --- > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > index 8173f709272be..e85625704d611 100644 > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > @@ -53,7 +53,9 @@ > > > > > #define DITHER_EN BIT(0) > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > { > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > + bool enable = false; > > > > > + > > > > > + /* default value for dither reg 5 to 14 */ > > > > > + const u32 dither_setting[] = { > > > > > + 0x00000000, /* 5 */ > > > > > + 0x00003002, /* 6 */ > > > > > + 0x00000000, /* 7 */ > > > > > + 0x00000000, /* 8 */ > > > > > + 0x00000000, /* 9 */ > > > > > + 0x00000000, /* 10 */ > > > > > + 0x00000000, /* 11 */ > > > > > + 0x00000011, /* 12 */ > > > > > + 0x00000000, /* 13 */ > > > > > + 0x00000000, /* 14 */ > > > > > > > > Could you explain what is this? > > > > > > this is dither 5 to dither 14 setting > > > this will be useless, we just need set dither 5 and dither 7 like > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > other value is same with hardware default value. > > > > > > > > > > > > > > > + }; > > > > > + > > > > > + if (bpc == 5 || bpc == 6) { > > > > > + enable = true; > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_NEW_BIT_MODE, > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > version is correct and previous version is incorrect? > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > mtk_dither_set() instead of duplication here. > > > > dither enable set in mtk_dither_set is > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > that is different 8183 and mt8192. > mt8173 dither enable in gamma is bit2 > mt8183 and mt8192 dither engine enable is bit 1 > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1. Is this reasonable? > > Regards, > > CK > > > > > > > > Regards, > > > > CK > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > + } > > > > > + > > > > > + > > > > > + if (enable) { > > > > > + u32 idx; > > > > > + > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > + DITHER_REG(idx + 5)); > > > > > + } > > > > > + > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > } > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97FF7C433E0 for ; Thu, 28 Jan 2021 08:20:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3298C64D9D for ; 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bh=D7f6UU2qkF6tlfnpAtMyZPF2/NarOHZ3GCaIjhXM6L0=; b=KNamYzp/ujaaDUvlrjQbKz/kO+qJ4kr8f+qUiRXKVuxIesTM5+s7IOrFtGS1wl5gb7 qcxU0GiVgq6WJy2n6ieDPu4Vtfq81TNU1z/VzXTsSmVy5cyRV63w1xA7lW72XsM9m/8s jw5LzUr+r4j3deluoDv4K7kNM/UwjkPnSqUCih4vI/iq+MtftS1mn51jL858+RIlVNf5 VPV/nv89L/N4TbUgLyJpKVFmMCn5/VeqEqS8xEfrbcylXCnMqUf3jDymKdYL7YndyWNa cEq2TmY+IJK1cX3e6NKTpYhdoLzdLxlfCwZDdezWwOaykZ4zrxgH5oytuSBMSEFLTWsK we2Q== X-Gm-Message-State: AOAM530wE87aRgPntcMcK/cPy2y07ERaXm65LLU91dsTS2xW17wMOXLm Az7NuyQ7BFxB5+MTSRczxgpfwZhsXoAGYjYLIOzfog== X-Google-Smtp-Source: ABdhPJy8CohiK7DuY6bT4ie39DRCyEWXlmXddonmwi5vsWuH4gheLsdx40UweC8SKCWBOA6AM66CZddl24p81cDx0hM= X-Received: by 2002:a05:6638:b12:: with SMTP id a18mr12268624jab.114.1611821948718; Thu, 28 Jan 2021 00:19:08 -0800 (PST) MIME-Version: 1.0 References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> In-Reply-To: <1611821396.1947.10.camel@mhfsdcap03> From: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:18:42 +0800 Message-ID: Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function To: Yongqiang Niu X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_031910_766111_B00DC801 X-CRM114-Status: GOOD ( 31.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , CK Hu , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > From: Yongqiang Niu > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > to improve the display quality > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > Signed-off-by: Hsin-Yi Wang > > > > > --- > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > index 8173f709272be..e85625704d611 100644 > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > @@ -53,7 +53,9 @@ > > > > > #define DITHER_EN BIT(0) > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > { > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > + bool enable = false; > > > > > + > > > > > + /* default value for dither reg 5 to 14 */ > > > > > + const u32 dither_setting[] = { > > > > > + 0x00000000, /* 5 */ > > > > > + 0x00003002, /* 6 */ > > > > > + 0x00000000, /* 7 */ > > > > > + 0x00000000, /* 8 */ > > > > > + 0x00000000, /* 9 */ > > > > > + 0x00000000, /* 10 */ > > > > > + 0x00000000, /* 11 */ > > > > > + 0x00000011, /* 12 */ > > > > > + 0x00000000, /* 13 */ > > > > > + 0x00000000, /* 14 */ > > > > > > > > Could you explain what is this? > > > > > > this is dither 5 to dither 14 setting > > > this will be useless, we just need set dither 5 and dither 7 like > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > other value is same with hardware default value. > > > > > > > > > > > > > > > + }; > > > > > + > > > > > + if (bpc == 5 || bpc == 6) { > > > > > + enable = true; > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_NEW_BIT_MODE, > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > version is correct and previous version is incorrect? > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > mtk_dither_set() instead of duplication here. > > > > dither enable set in mtk_dither_set is > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > that is different 8183 and mt8192. > mt8173 dither enable in gamma is bit2 > mt8183 and mt8192 dither engine enable is bit 1 > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1. Is this reasonable? > > Regards, > > CK > > > > > > > > Regards, > > > > CK > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > + } > > > > > + > > > > > + > > > > > + if (enable) { > > > > > + u32 idx; > > > > > + > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > + DITHER_REG(idx + 5)); > > > > > + } > > > > > + > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > } > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 774D3C433DB for ; Thu, 28 Jan 2021 19:45:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3270864E37 for ; Thu, 28 Jan 2021 19:45:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3270864E37 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FDC36EA12; Thu, 28 Jan 2021 19:44:39 +0000 (UTC) Received: from mail-io1-xd30.google.com (mail-io1-xd30.google.com [IPv6:2607:f8b0:4864:20::d30]) by gabe.freedesktop.org (Postfix) with ESMTPS id 61FE06E936 for ; Thu, 28 Jan 2021 08:19:09 +0000 (UTC) Received: by mail-io1-xd30.google.com with SMTP id q129so4718439iod.0 for ; Thu, 28 Jan 2021 00:19:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=D7f6UU2qkF6tlfnpAtMyZPF2/NarOHZ3GCaIjhXM6L0=; b=fjajd1fs13FXI1cwZk2oFUi5FQfh8MPatCfNKVQX6Cxj3tweQcGm5mhSnSW+p1zxGb oct6v7dmwRo82UfRdmMir/41Y5VGMNzFmlUpt8CXj/JY1M3tre7vlqU4kwz3wxP3WmJn bg1D+LQEK+KbPe6LYSC4IDGZ8dYPmZu3m+v20= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=D7f6UU2qkF6tlfnpAtMyZPF2/NarOHZ3GCaIjhXM6L0=; b=IDkrFPvMqmdm2g6hggw2mdYljBPZgG6efbxnerPWtpIdQVHFRXZ3HA63EsWWSYwY8p Izu+2j29Wa9z0umss/LtkKU0Rp+ZrNDoFpeOLYjllsBet/LgpQllpKVUGy8uOTBT39VC QO5SWi1Q+Ath1832cuppFwtTntn7ZDXllW2snA/hgVx0YfVU3wb/JkF/30LNIGj6hd9c 4jdpXoPS9tPk/2CimEATc11ifFkSPk0TAZ1NhkUlelnF9vmbnIqzSOUI8RnCY4YolH9c JxXHRI4t1wKocg6j/+l4gb0S59j/OWiMamLEogMHneC6a7xc1+DAaU3M04uAvPSy83pF eAmA== X-Gm-Message-State: AOAM531hnmRn5UkwVc0GZwTbZ9PgJpqNAE5P288JvmVReq3YoRs4AFTS Gzz9kttRrMnkTNLTDZZGVDfcGfJJ2USEkBE2EP5Flg== X-Google-Smtp-Source: ABdhPJy8CohiK7DuY6bT4ie39DRCyEWXlmXddonmwi5vsWuH4gheLsdx40UweC8SKCWBOA6AM66CZddl24p81cDx0hM= X-Received: by 2002:a05:6638:b12:: with SMTP id a18mr12268624jab.114.1611821948718; Thu, 28 Jan 2021 00:19:08 -0800 (PST) MIME-Version: 1.0 References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> In-Reply-To: <1611821396.1947.10.camel@mhfsdcap03> From: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:18:42 +0800 Message-ID: Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function To: Yongqiang Niu X-Mailman-Approved-At: Thu, 28 Jan 2021 19:44:35 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Devicetree List , David Airlie , lkml , dri-devel , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > From: Yongqiang Niu > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > to improve the display quality > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > Signed-off-by: Hsin-Yi Wang > > > > > --- > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > index 8173f709272be..e85625704d611 100644 > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > @@ -53,7 +53,9 @@ > > > > > #define DITHER_EN BIT(0) > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > { > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > + bool enable = false; > > > > > + > > > > > + /* default value for dither reg 5 to 14 */ > > > > > + const u32 dither_setting[] = { > > > > > + 0x00000000, /* 5 */ > > > > > + 0x00003002, /* 6 */ > > > > > + 0x00000000, /* 7 */ > > > > > + 0x00000000, /* 8 */ > > > > > + 0x00000000, /* 9 */ > > > > > + 0x00000000, /* 10 */ > > > > > + 0x00000000, /* 11 */ > > > > > + 0x00000011, /* 12 */ > > > > > + 0x00000000, /* 13 */ > > > > > + 0x00000000, /* 14 */ > > > > > > > > Could you explain what is this? > > > > > > this is dither 5 to dither 14 setting > > > this will be useless, we just need set dither 5 and dither 7 like > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > other value is same with hardware default value. > > > > > > > > > > > > > > > + }; > > > > > + > > > > > + if (bpc == 5 || bpc == 6) { > > > > > + enable = true; > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > + DITHER_NEW_BIT_MODE, > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > version is correct and previous version is incorrect? > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > mtk_dither_set() instead of duplication here. > > > > dither enable set in mtk_dither_set is > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > that is different 8183 and mt8192. > mt8173 dither enable in gamma is bit2 > mt8183 and mt8192 dither engine enable is bit 1 > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it will be set to bit2, but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it will be correct back to bit 1. Is this reasonable? > > Regards, > > CK > > > > > > > > Regards, > > > > CK > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > + } > > > > > + > > > > > + > > > > > + if (enable) { > > > > > + u32 idx; > > > > > + > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > + DITHER_REG(idx + 5)); > > > > > + } > > > > > + > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > } > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel