From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Rafael J. Wysocki" Subject: Re: [PATCH V8 5/6] ACPI: Support the probing on the devices which apply indirect-IO Date: Sat, 1 Apr 2017 11:52:04 +0200 Message-ID: References: <1490887619-61732-1-git-send-email-yuanzhichang@hisilicon.com> <1490887619-61732-6-git-send-email-yuanzhichang@hisilicon.com> <1908501.jAQQKvjW4f@aspire.rjw.lan> <58DDFCBE.1030705@hisilicon.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Received: from mail-oi0-f66.google.com ([209.85.218.66]:33306 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751297AbdDAJwG (ORCPT ); Sat, 1 Apr 2017 05:52:06 -0400 In-Reply-To: Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: "zhichang.yuan" Cc: "Rafael J. Wysocki" , "zhichang.yuan" , "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Rob Herring , Frank Rowand , Bjorn Helgaas , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , Mark Rutland , Brian Starkey , Olof Johansson , Lorenzo Pieralisi , Benjamin Herrenschmidt , Linux Kernel Mailing List , ACPI Devel Maling List , linuxar On Sat, Apr 1, 2017 at 4:16 AM, zhichang.yuan wrote: > > > On 04/01/2017 07:02 AM, Rafael J. Wysocki wrote: >> On Fri, Mar 31, 2017 at 8:52 AM, zhichang.yuan >> wrote: >>> Hi, Rafael, >>> >>> Thanks for reviewing this! >>> >>> On 2017/3/31 4:31, Rafael J. Wysocki wrote: >>>> On Thursday, March 30, 2017 11:26:58 PM zhichang.yuan wrote: >>>>> On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O >>>>> with some special host-local I/O ports known on x86. To access the I/O >>>>> peripherals, an indirect-IO mechanism is introduced to mapped the host-local >>>>> I/O to system logical/fake PIO similar the PCI MMIO on architectures where no >>>>> separate I/O space exists. Just as PCI MMIO, the host I/O range should be >>>>> registered before probing the downstream devices and set up the I/O mapping. >>>>> But current ACPI bus probing doesn't support these indirect-IO hosts/devices. >>>>> >>>>> This patch introdueces a new ACPI handler for this device category. Through the >>>>> handler attach callback, the indirect-IO hosts I/O registration is done and >>>>> all peripherals' I/O resources are translated into logic/fake PIO before >>>>> starting the enumeration. >>>> >>>> Can you explain to me briefly what exactly this code is expected to be doing? >>> >>> As you know currently for ARM architecture IO space is memory mapped and >>> is only used by pci devices. The port number is dynamically allocated >>> converting the device IO address into a PIO token: i.e. >>> http://lxr.free-electrons.com/source/drivers/acpi/pci_root.c#L745 >>> This patch is meant to support a new class of IO host controller >>> that are not PCI based and that still require to have the IO addresses >>> be translated in the same PIO token space as the PCI controller >> >> IOW, this is ARM-specific, right? > > Yes. The current host added in this patch with _HID "HISI0191" is on ARM64. But the underlying mechanism is ARM-specific as well AFAICS. > But, I think the handler driver is architecture dependent. I guess you mean "independent"? That doesn't matter. If ARM64 is the only architecture to use it in foreseeable future (which is the case for all I can say), it should go into acpi/arm64/ and please ask the maintainers thereof to review it. Thanks, Rafael From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751465AbdDAJwL (ORCPT ); Sat, 1 Apr 2017 05:52:11 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:33306 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751297AbdDAJwG (ORCPT ); Sat, 1 Apr 2017 05:52:06 -0400 MIME-Version: 1.0 In-Reply-To: References: <1490887619-61732-1-git-send-email-yuanzhichang@hisilicon.com> <1490887619-61732-6-git-send-email-yuanzhichang@hisilicon.com> <1908501.jAQQKvjW4f@aspire.rjw.lan> <58DDFCBE.1030705@hisilicon.com> From: "Rafael J. Wysocki" Date: Sat, 1 Apr 2017 11:52:04 +0200 X-Google-Sender-Auth: f1x1XaYu2Gu45H9Zbj41e7I5Fms Message-ID: Subject: Re: [PATCH V8 5/6] ACPI: Support the probing on the devices which apply indirect-IO To: "zhichang.yuan" Cc: "Rafael J. Wysocki" , "zhichang.yuan" , "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Rob Herring , Frank Rowand , Bjorn Helgaas , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , Mark Rutland , Brian Starkey , Olof Johansson , Lorenzo Pieralisi , Benjamin Herrenschmidt , Linux Kernel Mailing List , ACPI Devel Maling List , linuxarm@huawei.com, "devicetree@vger.kernel.org" , Linux PCI , Corey Minyard , Zou Rongrong , John Garry , Gabriele Paoloni , kantyzc@163.com, xuwei5@hisilicon.com Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Apr 1, 2017 at 4:16 AM, zhichang.yuan wrote: > > > On 04/01/2017 07:02 AM, Rafael J. Wysocki wrote: >> On Fri, Mar 31, 2017 at 8:52 AM, zhichang.yuan >> wrote: >>> Hi, Rafael, >>> >>> Thanks for reviewing this! >>> >>> On 2017/3/31 4:31, Rafael J. Wysocki wrote: >>>> On Thursday, March 30, 2017 11:26:58 PM zhichang.yuan wrote: >>>>> On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O >>>>> with some special host-local I/O ports known on x86. To access the I/O >>>>> peripherals, an indirect-IO mechanism is introduced to mapped the host-local >>>>> I/O to system logical/fake PIO similar the PCI MMIO on architectures where no >>>>> separate I/O space exists. Just as PCI MMIO, the host I/O range should be >>>>> registered before probing the downstream devices and set up the I/O mapping. >>>>> But current ACPI bus probing doesn't support these indirect-IO hosts/devices. >>>>> >>>>> This patch introdueces a new ACPI handler for this device category. Through the >>>>> handler attach callback, the indirect-IO hosts I/O registration is done and >>>>> all peripherals' I/O resources are translated into logic/fake PIO before >>>>> starting the enumeration. >>>> >>>> Can you explain to me briefly what exactly this code is expected to be doing? >>> >>> As you know currently for ARM architecture IO space is memory mapped and >>> is only used by pci devices. The port number is dynamically allocated >>> converting the device IO address into a PIO token: i.e. >>> http://lxr.free-electrons.com/source/drivers/acpi/pci_root.c#L745 >>> This patch is meant to support a new class of IO host controller >>> that are not PCI based and that still require to have the IO addresses >>> be translated in the same PIO token space as the PCI controller >> >> IOW, this is ARM-specific, right? > > Yes. The current host added in this patch with _HID "HISI0191" is on ARM64. But the underlying mechanism is ARM-specific as well AFAICS. > But, I think the handler driver is architecture dependent. I guess you mean "independent"? That doesn't matter. If ARM64 is the only architecture to use it in foreseeable future (which is the case for all I can say), it should go into acpi/arm64/ and please ask the maintainers thereof to review it. Thanks, Rafael From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: References: <1490887619-61732-1-git-send-email-yuanzhichang@hisilicon.com> <1490887619-61732-6-git-send-email-yuanzhichang@hisilicon.com> <1908501.jAQQKvjW4f@aspire.rjw.lan> <58DDFCBE.1030705@hisilicon.com> From: "Rafael J. Wysocki" Date: Sat, 1 Apr 2017 11:52:04 +0200 Message-ID: Subject: Re: [PATCH V8 5/6] ACPI: Support the probing on the devices which apply indirect-IO To: "zhichang.yuan" Cc: "Rafael J. Wysocki" , "zhichang.yuan" , "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Rob Herring , Frank Rowand , Bjorn Helgaas , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , Mark Rutland , Brian Starkey , Olof Johansson , Lorenzo Pieralisi , Benjamin Herrenschmidt , Linux Kernel Mailing List , ACPI Devel Maling List , linuxarm@huawei.com, "devicetree@vger.kernel.org" , Linux PCI , Corey Minyard , Zou Rongrong , John Garry , Gabriele Paoloni , kantyzc@163.com, xuwei5@hisilicon.com Content-Type: text/plain; charset=UTF-8 Sender: linux-acpi-owner@vger.kernel.org List-ID: On Sat, Apr 1, 2017 at 4:16 AM, zhichang.yuan wrote: > > > On 04/01/2017 07:02 AM, Rafael J. Wysocki wrote: >> On Fri, Mar 31, 2017 at 8:52 AM, zhichang.yuan >> wrote: >>> Hi, Rafael, >>> >>> Thanks for reviewing this! >>> >>> On 2017/3/31 4:31, Rafael J. Wysocki wrote: >>>> On Thursday, March 30, 2017 11:26:58 PM zhichang.yuan wrote: >>>>> On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O >>>>> with some special host-local I/O ports known on x86. To access the I/O >>>>> peripherals, an indirect-IO mechanism is introduced to mapped the host-local >>>>> I/O to system logical/fake PIO similar the PCI MMIO on architectures where no >>>>> separate I/O space exists. Just as PCI MMIO, the host I/O range should be >>>>> registered before probing the downstream devices and set up the I/O mapping. >>>>> But current ACPI bus probing doesn't support these indirect-IO hosts/devices. >>>>> >>>>> This patch introdueces a new ACPI handler for this device category. Through the >>>>> handler attach callback, the indirect-IO hosts I/O registration is done and >>>>> all peripherals' I/O resources are translated into logic/fake PIO before >>>>> starting the enumeration. >>>> >>>> Can you explain to me briefly what exactly this code is expected to be doing? >>> >>> As you know currently for ARM architecture IO space is memory mapped and >>> is only used by pci devices. The port number is dynamically allocated >>> converting the device IO address into a PIO token: i.e. >>> http://lxr.free-electrons.com/source/drivers/acpi/pci_root.c#L745 >>> This patch is meant to support a new class of IO host controller >>> that are not PCI based and that still require to have the IO addresses >>> be translated in the same PIO token space as the PCI controller >> >> IOW, this is ARM-specific, right? > > Yes. The current host added in this patch with _HID "HISI0191" is on ARM64. But the underlying mechanism is ARM-specific as well AFAICS. > But, I think the handler driver is architecture dependent. I guess you mean "independent"? That doesn't matter. If ARM64 is the only architecture to use it in foreseeable future (which is the case for all I can say), it should go into acpi/arm64/ and please ask the maintainers thereof to review it. Thanks, Rafael From mboxrd@z Thu Jan 1 00:00:00 1970 From: rafael@kernel.org (Rafael J. Wysocki) Date: Sat, 1 Apr 2017 11:52:04 +0200 Subject: [PATCH V8 5/6] ACPI: Support the probing on the devices which apply indirect-IO In-Reply-To: References: <1490887619-61732-1-git-send-email-yuanzhichang@hisilicon.com> <1490887619-61732-6-git-send-email-yuanzhichang@hisilicon.com> <1908501.jAQQKvjW4f@aspire.rjw.lan> <58DDFCBE.1030705@hisilicon.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sat, Apr 1, 2017 at 4:16 AM, zhichang.yuan wrote: > > > On 04/01/2017 07:02 AM, Rafael J. Wysocki wrote: >> On Fri, Mar 31, 2017 at 8:52 AM, zhichang.yuan >> wrote: >>> Hi, Rafael, >>> >>> Thanks for reviewing this! >>> >>> On 2017/3/31 4:31, Rafael J. Wysocki wrote: >>>> On Thursday, March 30, 2017 11:26:58 PM zhichang.yuan wrote: >>>>> On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O >>>>> with some special host-local I/O ports known on x86. To access the I/O >>>>> peripherals, an indirect-IO mechanism is introduced to mapped the host-local >>>>> I/O to system logical/fake PIO similar the PCI MMIO on architectures where no >>>>> separate I/O space exists. Just as PCI MMIO, the host I/O range should be >>>>> registered before probing the downstream devices and set up the I/O mapping. >>>>> But current ACPI bus probing doesn't support these indirect-IO hosts/devices. >>>>> >>>>> This patch introdueces a new ACPI handler for this device category. Through the >>>>> handler attach callback, the indirect-IO hosts I/O registration is done and >>>>> all peripherals' I/O resources are translated into logic/fake PIO before >>>>> starting the enumeration. >>>> >>>> Can you explain to me briefly what exactly this code is expected to be doing? >>> >>> As you know currently for ARM architecture IO space is memory mapped and >>> is only used by pci devices. The port number is dynamically allocated >>> converting the device IO address into a PIO token: i.e. >>> http://lxr.free-electrons.com/source/drivers/acpi/pci_root.c#L745 >>> This patch is meant to support a new class of IO host controller >>> that are not PCI based and that still require to have the IO addresses >>> be translated in the same PIO token space as the PCI controller >> >> IOW, this is ARM-specific, right? > > Yes. The current host added in this patch with _HID "HISI0191" is on ARM64. But the underlying mechanism is ARM-specific as well AFAICS. > But, I think the handler driver is architecture dependent. I guess you mean "independent"? That doesn't matter. If ARM64 is the only architecture to use it in foreseeable future (which is the case for all I can say), it should go into acpi/arm64/ and please ask the maintainers thereof to review it. Thanks, Rafael