[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
Use PLL1 sys clock for all operating points higher than 528MHz.

Note: For higher operating points VDD_SOC_IN needs to be 125mV
higher than the ARM set-point (see datasheet). Specifically, the
i.MX6UL/ULL EVK boards have an external DC regulator which needs
adjustment. The regulator adjustment is not covered with this
change.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 628fe899cb48..840f6386c780 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
 		 */
 		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
 		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
-		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
-			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
-		else
-			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
-		clk_set_parent(step_clk, secondary_sel_clk);
-		clk_set_parent(pll1_sw_clk, step_clk);
+		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
+			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
+				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
+			else
+				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
+			clk_set_parent(step_clk, secondary_sel_clk);
+			clk_set_parent(pll1_sw_clk, step_clk);
+		}
 	} else {
 		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 		clk_set_parent(pll1_sw_clk, step_clk);
-- 
2.15.1

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
Use PLL1 sys clock for all operating points higher than 528MHz.

Note: For higher operating points VDD_SOC_IN needs to be 125mV
higher than the ARM set-point (see datasheet). Specifically, the
i.MX6UL/ULL EVK boards have an external DC regulator which needs
adjustment. The regulator adjustment is not covered with this
change.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 628fe899cb48..840f6386c780 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
 		 */
 		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
 		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
-		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
-			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
-		else
-			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
-		clk_set_parent(step_clk, secondary_sel_clk);
-		clk_set_parent(pll1_sw_clk, step_clk);
+		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
+			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
+				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
+			else
+				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
+			clk_set_parent(step_clk, secondary_sel_clk);
+			clk_set_parent(pll1_sw_clk, step_clk);
+		}
 	} else {
 		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 		clk_set_parent(pll1_sw_clk, step_clk);
-- 
2.15.1

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Rafael J. Wysocki]

On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
> 
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

This makes sense to me, but I need someone with the requisite platform
knowledge to review it.

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>  		 */
>  		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>  		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -		else
> -			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -		clk_set_parent(step_clk, secondary_sel_clk);
> -		clk_set_parent(pll1_sw_clk, step_clk);
> +		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +			else
> +				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +			clk_set_parent(step_clk, secondary_sel_clk);
> +			clk_set_parent(pll1_sw_clk, step_clk);
> +		}
>  	} else {
>  		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>  		clk_set_parent(pll1_sw_clk, step_clk);
> 

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Rafael J. Wysocki]

On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
> 
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

This makes sense to me, but I need someone with the requisite platform
knowledge to review it.

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>  		 */
>  		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>  		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -		else
> -			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -		clk_set_parent(step_clk, secondary_sel_clk);
> -		clk_set_parent(pll1_sw_clk, step_clk);
> +		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +			else
> +				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +			clk_set_parent(step_clk, secondary_sel_clk);
> +			clk_set_parent(pll1_sw_clk, step_clk);
> +		}
>  	} else {
>  		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>  		clk_set_parent(pll1_sw_clk, step_clk);
> 

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

On 09.02.2018 12:52, Rafael J. Wysocki wrote:
> On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> This makes sense to me, but I need someone with the requisite platform
> knowledge to review it.
> 

Fabio, Leonard, maybe one of you could have a look at it?

It is similar to what ("cpufreq: imx: Add support for 700MHz setpoint in
cpufreq") in downstream is doing, it avoids changing pll twice though.

And, as mentioned in the commit log, the dc_reg part is missing. This is
because it is not required on our Colibri iMX6ULL since it uses a higher
(not switchable) VDD_SOC_IN voltage by default.

--
Stefan

>> ---
>>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>>  1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>>  		 */
>>  		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>>  		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> -		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> -			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> -		else
>> -			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> -		clk_set_parent(step_clk, secondary_sel_clk);
>> -		clk_set_parent(pll1_sw_clk, step_clk);
>> +		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> +			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> +				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> +			else
>> +				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> +			clk_set_parent(step_clk, secondary_sel_clk);
>> +			clk_set_parent(pll1_sw_clk, step_clk);
>> +		}
>>  	} else {
>>  		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>>  		clk_set_parent(pll1_sw_clk, step_clk);
>>

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

On 09.02.2018 12:52, Rafael J. Wysocki wrote:
> On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> This makes sense to me, but I need someone with the requisite platform
> knowledge to review it.
> 

Fabio, Leonard, maybe one of you could have a look at it?

It is similar to what ("cpufreq: imx: Add support for 700MHz setpoint in
cpufreq") in downstream is doing, it avoids changing pll twice though.

And, as mentioned in the commit log, the dc_reg part is missing. This is
because it is not required on our Colibri iMX6ULL since it uses a higher
(not switchable) VDD_SOC_IN voltage by default.

--
Stefan

>> ---
>>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>>  1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>>  		 */
>>  		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>>  		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> -		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> -			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> -		else
>> -			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> -		clk_set_parent(step_clk, secondary_sel_clk);
>> -		clk_set_parent(pll1_sw_clk, step_clk);
>> +		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> +			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> +				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> +			else
>> +				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> +			clk_set_parent(step_clk, secondary_sel_clk);
>> +			clk_set_parent(pll1_sw_clk, step_clk);
>> +		}
>>  	} else {
>>  		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>>  		clk_set_parent(pll1_sw_clk, step_clk);
>>

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Fabio Estevam]

Hi Anson,

On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>                  */
>                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -               else
> -                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -               clk_set_parent(step_clk, secondary_sel_clk);
> -               clk_set_parent(pll1_sw_clk, step_clk);
> +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +                               clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +                       else
> +                               clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +                       clk_set_parent(step_clk, secondary_sel_clk);
> +                       clk_set_parent(pll1_sw_clk, step_clk);
> +               }
>         } else {
>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);

Could you please help reviewing this patch?

Thanks

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Fabio Estevam]

Hi Anson,

On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>                  */
>                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -               else
> -                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -               clk_set_parent(step_clk, secondary_sel_clk);
> -               clk_set_parent(pll1_sw_clk, step_clk);
> +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +                               clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +                       else
> +                               clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +                       clk_set_parent(step_clk, secondary_sel_clk);
> +                       clk_set_parent(pll1_sw_clk, step_clk);
> +               }
>         } else {
>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);

Could you please help reviewing this patch?

Thanks

RE: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Anson Huang]

Anson Huang
Best Regards!


> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Sunday, February 11, 2018 12:26 AM
> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
> Cc: rjw@rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> linux-pm@vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
> max.oss.09@gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
> 
> Hi Anson,
> 
> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >
> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
> > EVK boards have an external DC regulator which needs adjustment. The
> > regulator adjustment is not covered with this change.
> >
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > ---
> >  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> >  1 file changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> > 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> >                  */
> >                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> >                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> > -               else
> > -                       clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > -               clk_set_parent(step_clk, secondary_sel_clk);
> > -               clk_set_parent(pll1_sw_clk, step_clk);
> > +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> > +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > +                               clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> > +                       else
> > +                               clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > +                       clk_set_parent(step_clk, secondary_sel_clk);
> > +                       clk_set_parent(pll1_sw_clk, step_clk);
> > +               }

For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see where sets ARM PLL rate?

Anson.

> >         } else {
> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >                 clk_set_parent(pll1_sw_clk, step_clk);
> 
> Could you please help reviewing this patch?
> 
> Thanks

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Anson Huang]

Anson Huang
Best Regards!


> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Sunday, February 11, 2018 12:26 AM
> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
> Cc: rjw at rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> linux-pm at vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
> max.oss.09 at gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
> 
> Hi Anson,
> 
> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >
> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
> > EVK boards have an external DC regulator which needs adjustment. The
> > regulator adjustment is not covered with this change.
> >
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > ---
> >  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> >  1 file changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> > 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> >                  */
> >                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> >                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> > -               else
> > -                       clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > -               clk_set_parent(step_clk, secondary_sel_clk);
> > -               clk_set_parent(pll1_sw_clk, step_clk);
> > +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> > +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > +                               clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> > +                       else
> > +                               clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > +                       clk_set_parent(step_clk, secondary_sel_clk);
> > +                       clk_set_parent(pll1_sw_clk, step_clk);
> > +               }

For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see where sets ARM PLL rate?

Anson.

> >         } else {
> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >                 clk_set_parent(pll1_sw_clk, step_clk);
> 
> Could you please help reviewing this patch?
> 
> Thanks

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

On 11.02.2018 02:42, Anson Huang wrote:
> Anson Huang
> Best Regards!
> 
> 
>> -----Original Message-----
>> From: Fabio Estevam [mailto:festevam@gmail.com]
>> Sent: Sunday, February 11, 2018 12:26 AM
>> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
>> Cc: rjw@rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
>> linux-pm@vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
>> max.oss.09@gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
>> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
>> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
>> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
>> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
>> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
>> i.MX6UL/ULL
>>
>> Hi Anson,
>>
>> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
>> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> > Use PLL1 sys clock for all operating points higher than 528MHz.
>> >
>> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
>> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
>> > EVK boards have an external DC regulator which needs adjustment. The
>> > regulator adjustment is not covered with this change.
>> >
>> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>> > ---
>> >  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> >  1 file changed, 8 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
>> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
>> > 100644
>> > --- a/drivers/cpufreq/imx6q-cpufreq.c
>> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
>> *policy, unsigned int index)
>> >                  */
>> >                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> >                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> > -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> > -               else
>> > -                       clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > -               clk_set_parent(step_clk, secondary_sel_clk);
>> > -               clk_set_parent(pll1_sw_clk, step_clk);
>> > +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> > +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > +                               clk_set_parent(secondary_sel_clk,
>> pll2_bus_clk);
>> > +                       else
>> > +                               clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > +                       clk_set_parent(step_clk, secondary_sel_clk);
>> > +                       clk_set_parent(pll1_sw_clk, step_clk);
>> > +               }
> 
> For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> where sets ARM PLL rate?

This is done unconditionally after the if statement:

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
			else
				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
			clk_set_parent(step_clk, secondary_sel_clk);
			clk_set_parent(pll1_sw_clk, step_clk);
		}
	} else {
		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
		clk_set_parent(pll1_sw_clk, step_clk);
		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
			clk_set_rate(pll1_sys_clk, new_freq * 1000);
			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(pll1_sys_clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(arm_clk, new_freq * 1000);


--
Stefan



> 
> Anson.
> 
>> >         } else {
>> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> >                 clk_set_parent(pll1_sw_clk, step_clk);
>>
>> Could you please help reviewing this patch?
>>
>> Thanks

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

On 11.02.2018 02:42, Anson Huang wrote:
> Anson Huang
> Best Regards!
> 
> 
>> -----Original Message-----
>> From: Fabio Estevam [mailto:festevam at gmail.com]
>> Sent: Sunday, February 11, 2018 12:26 AM
>> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
>> Cc: rjw at rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
>> linux-pm at vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
>> max.oss.09 at gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
>> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
>> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
>> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
>> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
>> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
>> i.MX6UL/ULL
>>
>> Hi Anson,
>>
>> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
>> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> > Use PLL1 sys clock for all operating points higher than 528MHz.
>> >
>> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
>> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
>> > EVK boards have an external DC regulator which needs adjustment. The
>> > regulator adjustment is not covered with this change.
>> >
>> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>> > ---
>> >  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> >  1 file changed, 8 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
>> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
>> > 100644
>> > --- a/drivers/cpufreq/imx6q-cpufreq.c
>> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
>> *policy, unsigned int index)
>> >                  */
>> >                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> >                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> > -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> > -               else
>> > -                       clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > -               clk_set_parent(step_clk, secondary_sel_clk);
>> > -               clk_set_parent(pll1_sw_clk, step_clk);
>> > +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> > +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > +                               clk_set_parent(secondary_sel_clk,
>> pll2_bus_clk);
>> > +                       else
>> > +                               clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > +                       clk_set_parent(step_clk, secondary_sel_clk);
>> > +                       clk_set_parent(pll1_sw_clk, step_clk);
>> > +               }
> 
> For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> where sets ARM PLL rate?

This is done unconditionally after the if statement:

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
			else
				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
			clk_set_parent(step_clk, secondary_sel_clk);
			clk_set_parent(pll1_sw_clk, step_clk);
		}
	} else {
		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
		clk_set_parent(pll1_sw_clk, step_clk);
		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
			clk_set_rate(pll1_sys_clk, new_freq * 1000);
			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(pll1_sys_clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(arm_clk, new_freq * 1000);


--
Stefan



> 
> Anson.
> 
>> >         } else {
>> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> >                 clk_set_parent(pll1_sw_clk, step_clk);
>>
>> Could you please help reviewing this patch?
>>
>> Thanks

RE: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Anson Huang]

Anson Huang
Best Regards!


> -----Original Message-----
> From: Stefan Agner [mailto:stefan@agner.ch]
> Sent: Monday, February 12, 2018 12:18 AM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>; rjw@rjwysocki.net; viresh kumar
> <viresh.kumar@linaro.org>; linux-pm@vger.kernel.org; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; max.oss.09@gmail.com; linux-kernel
> <linux-kernel@vger.kernel.org>; Octavian Purdila <octavian.purdila@nxp.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
> 
> On 11.02.2018 02:42, Anson Huang wrote:
> > Anson Huang
> > Best Regards!
> >
> >
> >> -----Original Message-----
> >> From: Fabio Estevam [mailto:festevam@gmail.com]
> >> Sent: Sunday, February 11, 2018 12:26 AM
> >> To: Stefan Agner <stefan@agner.ch>; Anson Huang
> <anson.huang@nxp.com>
> >> Cc: rjw@rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> >> linux-pm@vger.kernel.org; Marcel Ziswiler
> >> <marcel.ziswiler@toradex.com>; max.oss.09@gmail.com; linux-kernel
> >> <linux-kernel@vger.kernel.org>; Octavian Purdila
> >> <octavian.purdila@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> >> Shawn Guo <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX /
> >> MXC ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>;
> >> dl-linux-imx <linux-imx@nxp.com>
> >> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> >> i.MX6UL/ULL
> >>
> >> Hi Anson,
> >>
> >> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> >> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> >> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >> >
> >> > Note: For higher operating points VDD_SOC_IN needs to be 125mV
> >> > higher than the ARM set-point (see datasheet). Specifically, the
> >> > i.MX6UL/ULL EVK boards have an external DC regulator which needs
> >> > adjustment. The regulator adjustment is not covered with this change.
> >> >
> >> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> >> > ---
> >> >  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> >> >  1 file changed, 8 insertions(+), 6 deletions(-)
> >> >
> >> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> >> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> >> > 100644
> >> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> >> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> >> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct
> >> > cpufreq_policy
> >> *policy, unsigned int index)
> >> >                  */
> >> >                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> >> >                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> >> > -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> >> > -                       clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> >> > -               else
> >> > -                       clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > -               clk_set_parent(step_clk, secondary_sel_clk);
> >> > -               clk_set_parent(pll1_sw_clk, step_clk);
> >> > +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> >> > +                       if (freq_hz >
> clk_get_rate(pll2_pfd2_396m_clk))
> >> > +                               clk_set_parent(secondary_sel_clk,
> >> pll2_bus_clk);
> >> > +                       else
> >> > +                               clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > +                       clk_set_parent(step_clk, secondary_sel_clk);
> >> > +                       clk_set_parent(pll1_sw_clk, step_clk);
> >> > +               }
> >
> > For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> > where sets ARM PLL rate?
> 
> This is done unconditionally after the if statement:
> 
> 	if (of_machine_is_compatible("fsl,imx6ul") ||
> 	    of_machine_is_compatible("fsl,imx6ull")) {
> 		/*
> 		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
> 		 * CPU may run at higher than 528MHz, this will lead to
> 		 * the system unstable if the voltage is lower than the
> 		 * voltage of 528MHz, so lower the CPU frequency to one
> 		 * half before changing CPU frequency.
> 		 */
> 		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> 		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> 		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> 			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> 				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> 			else
> 				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> 			clk_set_parent(step_clk, secondary_sel_clk);
> 			clk_set_parent(pll1_sw_clk, step_clk);
> 		}
> 	} else {
> 		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> 		clk_set_parent(pll1_sw_clk, step_clk);
> 		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
> 			clk_set_rate(pll1_sys_clk, new_freq * 1000);
> 			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> 		} else {
> 			/* pll1_sys needs to be enabled for divider rate change to work.
> */
> 			pll1_sys_temp_enabled = true;
> 			clk_prepare_enable(pll1_sys_clk);
> 		}
> 	}
> 
> 	/* Ensure the arm clock divider is what we expect */
> 	ret = clk_set_rate(arm_clk, new_freq * 1000);
> 
> 
> --
> Stefan

Thanks, I see the CLK_SET_RATE_PARENT flag is set for arm clk.

Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
 
Anson.
> 
> 
> 
> >
> > Anson.
> >
> >> >         } else {
> >> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >> >                 clk_set_parent(pll1_sw_clk, step_clk);
> >>
> >> Could you please help reviewing this patch?
> >>
> >> Thanks

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Anson Huang]

Anson Huang
Best Regards!


> -----Original Message-----
> From: Stefan Agner [mailto:stefan at agner.ch]
> Sent: Monday, February 12, 2018 12:18 AM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>; rjw at rjwysocki.net; viresh kumar
> <viresh.kumar@linaro.org>; linux-pm at vger.kernel.org; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; max.oss.09 at gmail.com; linux-kernel
> <linux-kernel@vger.kernel.org>; Octavian Purdila <octavian.purdila@nxp.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
> 
> On 11.02.2018 02:42, Anson Huang wrote:
> > Anson Huang
> > Best Regards!
> >
> >
> >> -----Original Message-----
> >> From: Fabio Estevam [mailto:festevam at gmail.com]
> >> Sent: Sunday, February 11, 2018 12:26 AM
> >> To: Stefan Agner <stefan@agner.ch>; Anson Huang
> <anson.huang@nxp.com>
> >> Cc: rjw at rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> >> linux-pm at vger.kernel.org; Marcel Ziswiler
> >> <marcel.ziswiler@toradex.com>; max.oss.09 at gmail.com; linux-kernel
> >> <linux-kernel@vger.kernel.org>; Octavian Purdila
> >> <octavian.purdila@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> >> Shawn Guo <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX /
> >> MXC ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>;
> >> dl-linux-imx <linux-imx@nxp.com>
> >> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> >> i.MX6UL/ULL
> >>
> >> Hi Anson,
> >>
> >> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> >> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> >> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >> >
> >> > Note: For higher operating points VDD_SOC_IN needs to be 125mV
> >> > higher than the ARM set-point (see datasheet). Specifically, the
> >> > i.MX6UL/ULL EVK boards have an external DC regulator which needs
> >> > adjustment. The regulator adjustment is not covered with this change.
> >> >
> >> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> >> > ---
> >> >  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> >> >  1 file changed, 8 insertions(+), 6 deletions(-)
> >> >
> >> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> >> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> >> > 100644
> >> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> >> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> >> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct
> >> > cpufreq_policy
> >> *policy, unsigned int index)
> >> >                  */
> >> >                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> >> >                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> >> > -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> >> > -                       clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> >> > -               else
> >> > -                       clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > -               clk_set_parent(step_clk, secondary_sel_clk);
> >> > -               clk_set_parent(pll1_sw_clk, step_clk);
> >> > +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> >> > +                       if (freq_hz >
> clk_get_rate(pll2_pfd2_396m_clk))
> >> > +                               clk_set_parent(secondary_sel_clk,
> >> pll2_bus_clk);
> >> > +                       else
> >> > +                               clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > +                       clk_set_parent(step_clk, secondary_sel_clk);
> >> > +                       clk_set_parent(pll1_sw_clk, step_clk);
> >> > +               }
> >
> > For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> > where sets ARM PLL rate?
> 
> This is done unconditionally after the if statement:
> 
> 	if (of_machine_is_compatible("fsl,imx6ul") ||
> 	    of_machine_is_compatible("fsl,imx6ull")) {
> 		/*
> 		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
> 		 * CPU may run at higher than 528MHz, this will lead to
> 		 * the system unstable if the voltage is lower than the
> 		 * voltage of 528MHz, so lower the CPU frequency to one
> 		 * half before changing CPU frequency.
> 		 */
> 		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> 		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> 		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> 			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> 				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> 			else
> 				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> 			clk_set_parent(step_clk, secondary_sel_clk);
> 			clk_set_parent(pll1_sw_clk, step_clk);
> 		}
> 	} else {
> 		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> 		clk_set_parent(pll1_sw_clk, step_clk);
> 		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
> 			clk_set_rate(pll1_sys_clk, new_freq * 1000);
> 			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> 		} else {
> 			/* pll1_sys needs to be enabled for divider rate change to work.
> */
> 			pll1_sys_temp_enabled = true;
> 			clk_prepare_enable(pll1_sys_clk);
> 		}
> 	}
> 
> 	/* Ensure the arm clock divider is what we expect */
> 	ret = clk_set_rate(arm_clk, new_freq * 1000);
> 
> 
> --
> Stefan

Thanks, I see the CLK_SET_RATE_PARENT flag is set for arm clk.

Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
 
Anson.
> 
> 
> 
> >
> > Anson.
> >
> >> >         } else {
> >> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >> >                 clk_set_parent(pll1_sw_clk, step_clk);
> >>
> >> Could you please help reviewing this patch?
> >>
> >> Thanks

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Viresh Kumar]

On 19-01-18, 00:58, Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
> 
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>  		 */
>  		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>  		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -		else
> -			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -		clk_set_parent(step_clk, secondary_sel_clk);
> -		clk_set_parent(pll1_sw_clk, step_clk);
> +		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +			else
> +				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +			clk_set_parent(step_clk, secondary_sel_clk);
> +			clk_set_parent(pll1_sw_clk, step_clk);
> +		}
>  	} else {
>  		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>  		clk_set_parent(pll1_sw_clk, step_clk);

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

-- 
viresh

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Viresh Kumar]

On 19-01-18, 00:58, Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
> 
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>  		 */
>  		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>  		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -		else
> -			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -		clk_set_parent(step_clk, secondary_sel_clk);
> -		clk_set_parent(pll1_sw_clk, step_clk);
> +		if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +			if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +				clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +			else
> +				clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +			clk_set_parent(step_clk, secondary_sel_clk);
> +			clk_set_parent(pll1_sw_clk, step_clk);
> +		}
>  	} else {
>  		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>  		clk_set_parent(pll1_sw_clk, step_clk);

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

-- 
viresh

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Rafael J. Wysocki]

On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Can you please rebase this on top of 4.16-rc1?  It doesn't apply for me as is.

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>                  */
>                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -               else
> -                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -               clk_set_parent(step_clk, secondary_sel_clk);
> -               clk_set_parent(pll1_sw_clk, step_clk);
> +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +                               clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +                       else
> +                               clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +                       clk_set_parent(step_clk, secondary_sel_clk);
> +                       clk_set_parent(pll1_sw_clk, step_clk);
> +               }
>         } else {
>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);
> --
> 2.15.1
>

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Rafael J. Wysocki]

On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Can you please rebase this on top of 4.16-rc1?  It doesn't apply for me as is.

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>                  */
>                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> -               else
> -                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> -               clk_set_parent(step_clk, secondary_sel_clk);
> -               clk_set_parent(pll1_sw_clk, step_clk);
> +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> +                               clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> +                       else
> +                               clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> +                       clk_set_parent(step_clk, secondary_sel_clk);
> +                       clk_set_parent(pll1_sw_clk, step_clk);
> +               }
>         } else {
>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);
> --
> 2.15.1
>

Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

On 12.02.2018 11:18, Rafael J. Wysocki wrote:
> On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> Can you please rebase this on top of 4.16-rc1?  It doesn't apply for me as is.
> 

Oh I see, Anson actually already submitted a patch which makes higher
CPU rates working.

My solution is slightly different in that it avoids unnecessary parent
changes...

I will rework this patch to apply this simplification to the current
state of the driver.

--
Stefan


>> ---
>>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>>  1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>>                  */
>>                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>>                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> -               else
>> -                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> -               clk_set_parent(step_clk, secondary_sel_clk);
>> -               clk_set_parent(pll1_sw_clk, step_clk);
>> +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> +                               clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> +                       else
>> +                               clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> +                       clk_set_parent(step_clk, secondary_sel_clk);
>> +                       clk_set_parent(pll1_sw_clk, step_clk);
>> +               }
>>         } else {
>>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>>                 clk_set_parent(pll1_sw_clk, step_clk);
>> --
>> 2.15.1
>>

[PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL

[Stefan Agner]

On 12.02.2018 11:18, Rafael J. Wysocki wrote:
> On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> Can you please rebase this on top of 4.16-rc1?  It doesn't apply for me as is.
> 

Oh I see, Anson actually already submitted a patch which makes higher
CPU rates working.

My solution is slightly different in that it avoids unnecessary parent
changes...

I will rework this patch to apply this simplification to the current
state of the driver.

--
Stefan


>> ---
>>  drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>>  1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>>                  */
>>                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>>                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> -               if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> -                       clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> -               else
>> -                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> -               clk_set_parent(step_clk, secondary_sel_clk);
>> -               clk_set_parent(pll1_sw_clk, step_clk);
>> +               if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> +                       if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> +                               clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> +                       else
>> +                               clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> +                       clk_set_parent(step_clk, secondary_sel_clk);
>> +                       clk_set_parent(pll1_sw_clk, step_clk);
>> +               }
>>         } else {
>>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>>                 clk_set_parent(pll1_sw_clk, step_clk);
>> --
>> 2.15.1
>>