From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933814AbeBLKSl (ORCPT ); Mon, 12 Feb 2018 05:18:41 -0500 Received: from mail-ot0-f194.google.com ([74.125.82.194]:42403 "EHLO mail-ot0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932663AbeBLKSf (ORCPT ); Mon, 12 Feb 2018 05:18:35 -0500 X-Google-Smtp-Source: AH8x225kLB5a1mTJeUHJjW6R2DuAuSHESNc52UxDCMf9IIqfPry6PffZU+tqje0V2o23n1RRX+LiUgfUFXXAL6ZA2co= MIME-Version: 1.0 In-Reply-To: <20180118235836.17393-1-stefan@agner.ch> References: <20180118235836.17393-1-stefan@agner.ch> From: "Rafael J. Wysocki" Date: Mon, 12 Feb 2018 11:18:33 +0100 X-Google-Sender-Auth: FozawTatXDGPsKDFTUhXRjUHme8 Message-ID: Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL To: Stefan Agner Cc: "Rafael J. Wysocki" , Viresh Kumar , Fabio Estevam , Octavian Purdila , Shawn Guo , max.oss.09@gmail.com, marcel.ziswiler@toradex.com, Linux PM , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner wrote: > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz. > Use PLL1 sys clock for all operating points higher than 528MHz. > > Note: For higher operating points VDD_SOC_IN needs to be 125mV > higher than the ARM set-point (see datasheet). Specifically, the > i.MX6UL/ULL EVK boards have an external DC regulator which needs > adjustment. The regulator adjustment is not covered with this > change. > > Signed-off-by: Stefan Agner Can you please rebase this on top of 4.16-rc1? It doesn't apply for me as is. > --- > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c > index 628fe899cb48..840f6386c780 100644 > --- a/drivers/cpufreq/imx6q-cpufreq.c > +++ b/drivers/cpufreq/imx6q-cpufreq.c > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) > */ > clk_set_rate(arm_clk, (old_freq >> 1) * 1000); > clk_set_parent(pll1_sw_clk, pll1_sys_clk); > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) > - clk_set_parent(secondary_sel_clk, pll2_bus_clk); > - else > - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); > - clk_set_parent(step_clk, secondary_sel_clk); > - clk_set_parent(pll1_sw_clk, step_clk); > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) { > + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) > + clk_set_parent(secondary_sel_clk, pll2_bus_clk); > + else > + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); > + clk_set_parent(step_clk, secondary_sel_clk); > + clk_set_parent(pll1_sw_clk, step_clk); > + } > } else { > clk_set_parent(step_clk, pll2_pfd2_396m_clk); > clk_set_parent(pll1_sw_clk, step_clk); > -- > 2.15.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: rafael@kernel.org (Rafael J. Wysocki) Date: Mon, 12 Feb 2018 11:18:33 +0100 Subject: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL In-Reply-To: <20180118235836.17393-1-stefan@agner.ch> References: <20180118235836.17393-1-stefan@agner.ch> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner wrote: > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz. > Use PLL1 sys clock for all operating points higher than 528MHz. > > Note: For higher operating points VDD_SOC_IN needs to be 125mV > higher than the ARM set-point (see datasheet). Specifically, the > i.MX6UL/ULL EVK boards have an external DC regulator which needs > adjustment. The regulator adjustment is not covered with this > change. > > Signed-off-by: Stefan Agner Can you please rebase this on top of 4.16-rc1? It doesn't apply for me as is. > --- > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c > index 628fe899cb48..840f6386c780 100644 > --- a/drivers/cpufreq/imx6q-cpufreq.c > +++ b/drivers/cpufreq/imx6q-cpufreq.c > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) > */ > clk_set_rate(arm_clk, (old_freq >> 1) * 1000); > clk_set_parent(pll1_sw_clk, pll1_sys_clk); > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) > - clk_set_parent(secondary_sel_clk, pll2_bus_clk); > - else > - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); > - clk_set_parent(step_clk, secondary_sel_clk); > - clk_set_parent(pll1_sw_clk, step_clk); > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) { > + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) > + clk_set_parent(secondary_sel_clk, pll2_bus_clk); > + else > + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); > + clk_set_parent(step_clk, secondary_sel_clk); > + clk_set_parent(pll1_sw_clk, step_clk); > + } > } else { > clk_set_parent(step_clk, pll2_pfd2_396m_clk); > clk_set_parent(pll1_sw_clk, step_clk); > -- > 2.15.1 >