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From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Alison Schofield <alison.schofield@intel.com>,
	Erik Kaneda <erik.kaneda@intel.com>,
	Linux PCI <linux-pci@vger.kernel.org>,
	ACPI Devel Maling List <linux-acpi@vger.kernel.org>
Subject: Re: [PATCH v5 1/6] cxl/acpi: Local definition of ACPICA infrastructure
Date: Mon, 7 Jun 2021 14:25:48 +0200	[thread overview]
Message-ID: <CAJZ5v0jhh8EXNY9C1_HpD7tdW9s5uNkKdyLOEDAgeK4yHpFXdA@mail.gmail.com> (raw)
In-Reply-To: <162295949886.1109360.17423894188288323907.stgit@dwillia2-desk3.amr.corp.intel.com>

On Sun, Jun 6, 2021 at 8:05 AM Dan Williams <dan.j.williams@intel.com> wrote:
>
> The recently released CXL specification change (ECN) for the CXL Fixed
> Memory Window Structure (CFMWS) extension to the CXL Early Discovery
> Table (CEDT) enables a large amount of functionality. It defines the
> root of a CXL memory topology and is needed for all OS flows for CXL
> provisioning CXL memory expanders. For ease of merging and tree
> management add the new ACPI definition locally (drivers/cxl/acpi.h) in
> such a way that they will not collide with the eventual arrival of the
> definitions through the ACPICA project to their final location
> (drivers/acpi/actbl1.h).

I've just applied the ACPICA series including this change which can be
made available as a forward-only branch in my tree, if that helps.

> The definitions in drivers/cxl/acpi.h can be dropped post -rc1.
>
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Co-developed-by: Alison Schofield <alison.schofield@intel.com>
> Co-developed-by: Erik Kaneda <erik.kaneda@intel.com>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
>  drivers/cxl/acpi.h |   48 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
>  create mode 100644 drivers/cxl/acpi.h
>
> diff --git a/drivers/cxl/acpi.h b/drivers/cxl/acpi.h
> new file mode 100644
> index 000000000000..1482c19e7227
> --- /dev/null
> +++ b/drivers/cxl/acpi.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* Copyright(c) 2021 Intel Corporation. */
> +#ifndef __CXL_ACPI_H__
> +#define __CXL_ACPI_H__
> +
> +#ifndef ACPI_CEDT_CHBS_VERSION_CXL20
> +/*
> + * NOTE: These definitions are temporary and to be deleted in v5.14-rc1
> + * when the identical definitions become available from
> + * include/acpi/actbl1.h.
> + */
> +
> +#define ACPI_CEDT_TYPE_CFMWS 1
> +#define ACPI_CEDT_TYPE_RESERVED 2
> +
> +#define ACPI_CEDT_CHBS_VERSION_CXL11 (0)
> +#define ACPI_CEDT_CHBS_VERSION_CXL20 (1)
> +
> +#define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000)
> +#define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000)
> +
> +struct acpi_cedt_cfmws {
> +       struct acpi_cedt_header header;
> +       u32 reserved1;
> +       u64 base_hpa;
> +       u64 window_size;
> +       u8 interleave_ways;
> +       u8 interleave_arithmetic;
> +       u16 reserved2;
> +       u32 granularity;
> +       u16 restrictions;
> +       u16 qtg_id;
> +       u32 interleave_targets[];
> +};
> +
> +/* Values for Interleave Arithmetic field above */
> +
> +#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
> +
> +/* Values for Restrictions field above */
> +
> +#define ACPI_CEDT_CFMWS_RESTRICT_TYPE2 (1)
> +#define ACPI_CEDT_CFMWS_RESTRICT_TYPE3 (1 << 1)
> +#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1 << 2)
> +#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1 << 3)
> +#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1 << 4)
> +#endif /* ACPI_CEDT_CHBS_VERSION_CXL20 */
> +#endif /* __CXL_ACPI_H__ */
>

  reply	other threads:[~2021-06-07 12:26 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-06  6:04 [PATCH v5 0/6] CXL port and decoder enumeration Dan Williams
2021-06-06  6:04 ` [PATCH v5 1/6] cxl/acpi: Local definition of ACPICA infrastructure Dan Williams
2021-06-07 12:25   ` Rafael J. Wysocki [this message]
2021-06-07 17:03     ` Dan Williams
2021-06-08 18:13       ` Dan Williams
2021-06-08 19:29         ` Rafael J. Wysocki
2021-06-06  6:05 ` [PATCH v5 2/6] cxl/acpi: Introduce cxl_root, the root of a cxl_port topology Dan Williams
2021-06-07 12:27   ` Rafael J. Wysocki
2021-06-07 22:18   ` Ben Widawsky
2021-06-08 11:28   ` Jonathan Cameron
2021-06-08 20:03     ` Dan Williams
2021-06-06  6:05 ` [PATCH v5 3/6] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS Dan Williams
2021-06-06  6:05 ` [PATCH v5 4/6] cxl/acpi: Add downstream port data to cxl_port instances Dan Williams
2021-06-08 11:49   ` Jonathan Cameron
2021-06-08 23:58     ` Dan Williams
2021-06-09 11:28       ` Jonathan Cameron
2021-06-09 15:15         ` Dan Williams
2021-06-06  6:05 ` [PATCH v5 5/6] cxl/acpi: Enumerate host bridge root ports Dan Williams
2021-06-08 12:42   ` Jonathan Cameron
2021-06-06  6:05 ` [PATCH v5 6/6] cxl/acpi: Introduce cxl_decoder objects Dan Williams
2021-06-08 13:06   ` Jonathan Cameron
2021-06-08 23:48     ` Dan Williams

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