From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D71B2C433F5 for ; Thu, 13 Jan 2022 23:35:33 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 49A79832EA; Fri, 14 Jan 2022 00:35:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QA8z2cqB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A5B4C83384; Fri, 14 Jan 2022 00:35:29 +0100 (CET) Received: from mail-yb1-xb35.google.com (mail-yb1-xb35.google.com [IPv6:2607:f8b0:4864:20::b35]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 426E4832EA for ; Fri, 14 Jan 2022 00:35:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=mibodhi@gmail.com Received: by mail-yb1-xb35.google.com with SMTP id c10so19650329ybb.2 for ; Thu, 13 Jan 2022 15:35:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=E6HH537mKOivdFiDod0Miv1VXShUqu8cbTBYtccM+90=; b=QA8z2cqBA1uGbrkG91BfiYT/ISR1HS9m7I+4usHUrcBvYAFV6PaGAF96IMC+WuMn7B DQ0IFed0mk+bbcTcv85s8OZUyzKDpyqvCNfVGOxAA+d46elmn96lVgQKkUI5G1H+Q/JH l4Qp7hJRGDg5TqtZSoMNBKeCkbUu4l3swg9Oc50rZmogc2eLBzE1Lf3U55yCPCTGsQ92 lcElNoO9V6LdY0ZR/TLKBTOlmbk+qQmfjuE+79CxRSem7Ne3CYwBoBEo7/jGe/jUx0Vn s5B19ZOZOFEeLVqMEh1VtbAQDb283urWHRrcjjtIMd7uWI0wMVGPVFWCcr54GlMZYtzG Dgxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=E6HH537mKOivdFiDod0Miv1VXShUqu8cbTBYtccM+90=; b=dtacWdbEqWJ5pn2TraYEKYoWbrd88rCmLRwSXJX+J5DpYzdn+PM9QPVsFprFlMTlay Bib9MrLuBUteQ1P5UVfm/OemfQWj9fV8UPtRD/U1dzdMwdH+n1oybkuN1E4x408PUGz3 EoC+7O6NmXgnGzyHP6iwgMNgo61/lw+bVfAQpoIxoVw8raxbEzldvdoI37UAS5IWWeo/ M0vZKD1vwj7KnpzetJY0msxbaif3410mWzjShPB/F+/SB6ajfCuZtidyQCSyJH+2xB1R mzgaRw35WjVHiPBKnVuAfN2QO/pkMCjvlCirc0PPtZOMVQ7kSsI08rNWXloftpXnrwEn +OuQ== X-Gm-Message-State: AOAM530cKTkUwpS+IQt7zXfbzfpa3VsmUkn0DKPCFXyHvPa5Rx0O32zs qcW79N0K/xlrQPI6RZdYjw9LIoep3HUoaQR31IY= X-Google-Smtp-Source: ABdhPJxNSRt+UB6yT5faJrv81CD8z7uCp4GKkQH3K9FMZ5tmKESPxOkSB51VjVCP8UErgmLYmmD73opAxcpUDXYd6EY= X-Received: by 2002:a25:7ac5:: with SMTP id v188mr9352223ybc.246.1642116924898; Thu, 13 Jan 2022 15:35:24 -0800 (PST) MIME-Version: 1.0 References: <20220113132804.7814-1-pali@kernel.org> In-Reply-To: <20220113132804.7814-1-pali@kernel.org> From: Tony Dinh Date: Thu, 13 Jan 2022 15:35:13 -0800 Message-ID: Subject: Re: [PATCH] pci: pci_mvebu: Add support for Kirkwood PCIe controllers To: =?UTF-8?Q?Pali_Roh=C3=A1r?= Cc: Stefan Roese , U-Boot Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Pali, On Thu, Jan 13, 2022 at 5:28 AM Pali Roh=C3=A1r wrote: > > Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base > address of PCIe mappings. Size of PCIe windows is not defined in any macr= o > yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SI= ZE > macros. > > Kirkwood arch code already maps mbus windows for io and mem, so avoid > calling mvebu_mbus_add_window_by_id() function which would try to do > duplicate window mapping. > > Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatib= le > string, so mark pci_mvebu.c driver as compatible for it. > > Signed-off-by: Pali Roh=C3=A1r > --- > This patch depends on series "mvebu: Move PCIe code from serdes to PCIe d= river": > https://patchwork.ozlabs.org/project/uboot/list/?series=3D277906&state=3D= * > > Tony, could you please test it in Kirwood hardware? Thanks for sending in this patch. I'll run some tests and let you know. Tony > --- > arch/arm/mach-kirkwood/cpu.c | 4 ++-- > arch/arm/mach-kirkwood/include/mach/cpu.h | 3 +++ > drivers/pci/Kconfig | 6 +++--- > drivers/pci/pci_mvebu.c | 16 ++++++++++++++++ > 4 files changed, 24 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c > index e9571298a824..80f893ab369a 100644 > --- a/arch/arm/mach-kirkwood/cpu.c > +++ b/arch/arm/mach-kirkwood/cpu.c > @@ -54,11 +54,11 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval= ) > > static struct mbus_win windows[] =3D { > /* Window 0: PCIE MEM address space */ > - { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, > + { KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE, > KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, > > /* Window 1: PCIE IO address space */ > - { KW_DEFADR_PCI_IO, 1024 * 64, > + { KW_DEFADR_PCI_IO, KW_DEFADR_PCI_IO_SIZE, > KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO }, > > /* Window 2: NAND Flash address space */ > diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-ki= rkwood/include/mach/cpu.h > index ea42182cf9c6..71c546f9acf6 100644 > --- a/arch/arm/mach-kirkwood/include/mach/cpu.h > +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h > @@ -68,6 +68,9 @@ enum kwcpu_attrib { > #define KW_DEFADR_SPIF 0xE8000000 > #define KW_DEFADR_BOOTROM 0xF8000000 > > +#define KW_DEFADR_PCI_MEM_SIZE (1024 * 1024 * 256) > +#define KW_DEFADR_PCI_IO_SIZE (1024 * 64) > + > struct mbus_win { > u32 base; > u32 size; > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > index 630d6e6cc5ee..69141344c869 100644 > --- a/drivers/pci/Kconfig > +++ b/drivers/pci/Kconfig > @@ -262,13 +262,13 @@ config PCIE_IPROC > Say Y here if you want to enable Broadcom iProc PCIe controller= , > > config PCI_MVEBU > - bool "Enable Armada XP/38x PCIe driver" > - depends on ARCH_MVEBU > + bool "Enable Kirkwood / Armada 370/XP/375/38x PCIe driver" > + depends on (ARCH_KIRKWOOD || ARCH_MVEBU) > select MISC > select DM_RESET > help > Say Y here if you want to enable PCIe controller support on > - Armada XP/38x SoCs. > + Kirkwood and Armada 370/XP/375/38x SoCs. > > config PCIE_DW_COMMON > bool > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c > index b3ea034a2847..d99a99bae940 100644 > --- a/drivers/pci/pci_mvebu.c > +++ b/drivers/pci/pci_mvebu.c > @@ -498,6 +498,13 @@ static int mvebu_pcie_probe(struct udevice *dev) > mvebu_pcie_set_local_bus_nr(pcie, 0); > mvebu_pcie_set_local_dev_nr(pcie, 1); > > + /* > + * Kirkwood arch code already maps mbus windows for PCIe IO and M= EM. > + * So skip calling mvebu_mbus_add_window_by_id() function as it w= ould > + * fail on error "conflicts with another window" which means conf= lict > + * with existing PCIe window mappings. > + */ > +#ifndef CONFIG_ARCH_KIRKWOOD > if (resource_size(&pcie->mem) && > mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr, > (phys_addr_t)pcie->mem.start, > @@ -519,6 +526,7 @@ static int mvebu_pcie_probe(struct udevice *dev) > pcie->io.start =3D 0; > pcie->io.end =3D -1; > } > +#endif > > /* Setup windows and configure host bridge */ > mvebu_pcie_setup_wins(pcie); > @@ -725,10 +733,17 @@ static int mvebu_pcie_bind(struct udevice *parent) > } > ports_count =3D 0; > > +#ifdef CONFIG_ARCH_KIRKWOOD > + mem.start =3D KW_DEFADR_PCI_MEM; > + mem.end =3D KW_DEFADR_PCI_MEM + KW_DEFADR_PCI_MEM_SIZE - 1; > + io.start =3D KW_DEFADR_PCI_IO; > + io.end =3D KW_DEFADR_PCI_IO + KW_DEFADR_PCI_IO_SIZE - 1; > +#else > mem.start =3D MBUS_PCI_MEM_BASE; > mem.end =3D MBUS_PCI_MEM_BASE + MBUS_PCI_MEM_SIZE - 1; > io.start =3D MBUS_PCI_IO_BASE; > io.end =3D MBUS_PCI_IO_BASE + MBUS_PCI_IO_SIZE - 1; > +#endif > > /* First phase: Fill mvebu_pcie struct for each port */ > ofnode_for_each_subnode(subnode, dev_ofnode(parent)) { > @@ -809,6 +824,7 @@ static int mvebu_pcie_bind(struct udevice *parent) > static const struct udevice_id mvebu_pcie_ids[] =3D { > { .compatible =3D "marvell,armada-xp-pcie" }, > { .compatible =3D "marvell,armada-370-pcie" }, > + { .compatible =3D "marvell,kirkwood-pcie" }, > { } > }; > > -- > 2.20.1 >