From: jaswinder.singh@linaro.org (Jassi Brar)
To: linux-arm-kernel@lists.infradead.org
Subject: SPI subsystem delays
Date: Mon, 23 Apr 2012 14:05:54 +0530 [thread overview]
Message-ID: <CAJe_ZheQZFA_wuCPa+reHU3HOGku-iiQh-GjJOy6Xr=c+ExGiQ@mail.gmail.com> (raw)
In-Reply-To: <CADjezmaB7yo6W1dW11JKtH7JNSsgXQvOQy5BMqtAUfe6sy2igA@mail.gmail.com>
On 23 April 2012 02:37, Matt Wood <mattwood2000@gmail.com> wrote:
>
> has some specific delay requirements - specifically
> the delay between bytes in a single transfer
>
Sounds like your chip specific quirk. Apparently throughput would
be the last of your concerns :D
Perhaps you have to do single byte transfers with appropriate
non-zero 'delay_usecs' and skilfully toggle 'cs_change' for
each transfer.
> delay between chip select assertion and the first clock edge
>
IMO that could already be done from within your controller driver.
> and the delay between consecutive transfers.
>
Why not spi_transfer.delay_usecs ?
-jassi
next prev parent reply other threads:[~2012-04-23 8:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-22 21:07 SPI subsystem delays Matt Wood
2012-04-23 8:35 ` Jassi Brar [this message]
2012-04-23 15:20 ` Matt Wood
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