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Date: Sat, 15 Oct 2011 16:55:43 +0530
Message-ID: <CAJe_ZheocjVhD4PTXQo3R7rqgiyt4BCo8Fx_sJ7AmDCjB=zMxQ@mail.gmail.com>
Subject: Re: [PATCHv4] DMAEngine: Define interleaved transfer request api
From: Jassi Brar <jaswinder.singh@linaro.org>
To: "Bounine, Alexandre" <Alexandre.Bounine@idt.com>
Cc: "Williams, Dan J" <dan.j.williams@intel.com>,
        Vinod Koul <vinod.koul@intel.com>, Russell King <rmk@arm.linux.org.uk>,
        Barry Song <21cnbao@gmail.com>, linux-kernel@vger.kernel.org,
        DL-SHA-WorkGroupLinux <workgroup.linux@csr.com>,
        Dave Jiang <dave.jiang@intel.com>
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On 15 October 2011 00:45, Bounine, Alexandre <Alexandre.Bounine@idt.com> wrote:

>> But doesn't the info, pointed to by this (void *), remain same for
>> every
>> transfer to a particular target/remote device ?
> No. An address within the target may (and most likely will) be changed for
> every transfer. Target destination ID will be the same for given virtual channel.
>
Thanks for the info.

> Virtual channel may bring the same challenge and I may need a channel locking
> if more than one requester try to read/write data to the same target RIO device.
>
One can't avoid taking care of locking, but using virtual channels keeps
the dma_chan usage consistent.

RapidIO supports 34(32+2), 50(48+2) and 66(64+2) bit addressing
which makes me wonder if the (upper or lower) 2 bits could be attached to
the identity of the target device ?
(tsi721 driver actually discards the upper 2 bits while claiming to support
66bit addressing so I couldn't make anything out of it and specs don't
seem to say much about it)

If there is no user of 66bit addressing and isn't coming in very near future,
we might as well drop that case for now(tsi721 already does) because
that 'completeness' of support modifies the semantics of dmaengine apis
today for no real use.