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From: Evan M <etm2131@columbia.edu>
To: qemu-riscv@nongnu.org
Subject: medeleg[11] should be hardwired to zero?
Date: Fri, 9 Apr 2021 16:15:04 -0400	[thread overview]
Message-ID: <CAJh8_PvnRWh9Ki+Jc6ZKibq64P-Khv85pjTJUcuEJS5OOQB8bA@mail.gmail.com> (raw)

Hi,

I'm relatively new to RISC-V, so this may be a misunderstanding on my
part. According to the privileged ISA spec v1.12-draft,

> For exceptions that cannot occur in less privileged modes, the corresponding medeleg bits
> should be hardwired to zero. In particular, medeleg[11] is hardwired to zero.

This bit corresponds to RISCV_EXCP_M_ECALL in QEMU, which is OR'd into
delegable_excps in target/riscv/csr.c. Indeed, I can set bit 11
running an RV64 target in QEMU.

Is this a bug in QEMU or a misunderstanding on my part? I'm having a
hard time finding exactly where in the spec it enumerates which
interrupts and exceptions can be delegated from M mode to S mode, so
perhaps I'm off base.

Thanks,
Evan

-- 
Evan Mesterhazy
etm2131@columbia.edu


                 reply	other threads:[~2021-04-09 20:16 UTC|newest]

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