From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bvo8V-00005Z-Co for qemu-devel@nongnu.org; Sun, 16 Oct 2016 12:18:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bvo8U-0007Li-Hi for qemu-devel@nongnu.org; Sun, 16 Oct 2016 12:18:07 -0400 Received: from mail-io0-x244.google.com ([2607:f8b0:4001:c06::244]:34036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bvo8U-0007LP-Ck for qemu-devel@nongnu.org; Sun, 16 Oct 2016 12:18:06 -0400 Received: by mail-io0-x244.google.com with SMTP id i202so9599608ioi.1 for ; Sun, 16 Oct 2016 09:18:06 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20161016084755.GA11739@stefanha-x1.localdomain> References: <20160714202026.9727-1-bobby.prani@gmail.com> <20160714202026.9727-9-bobby.prani@gmail.com> <20161016084755.GA11739@stefanha-x1.localdomain> From: Pranith Kumar Date: Sun, 16 Oct 2016 12:17:35 -0400 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v4 08/14] tcg/s390: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Hajnoczi Cc: Alexander Graf , Richard Henderson , "open list:All patches CC here" , Peter Maydell , Sergey Fedorov , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Paolo Bonzini On Sun, Oct 16, 2016 at 4:47 AM, Stefan Hajnoczi wrote: > On Thu, Jul 14, 2016 at 04:20:20PM -0400, Pranith Kumar wrote: >> Cc: Alexander Graf >> Signed-off-by: Pranith Kumar >> Signed-off-by: Richard Henderson >> --- >> tcg/s390/tcg-target.inc.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c >> index 5a7495b..01aae35 100644 >> --- a/tcg/s390/tcg-target.inc.c >> +++ b/tcg/s390/tcg-target.inc.c >> @@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr; >> #define FACILITY_EXT_IMM (1ULL << (63 - 21)) >> #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) >> #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) >> +#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND >> >> static uint64_t facilities; >> >> @@ -2172,6 +2173,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, >> tgen_deposit(s, args[0], args[2], args[3], args[4]); >> break; >> >> + case INDEX_op_mb: >> + /* The host memory model is quite strong, we simply need to >> + serialize the instruction stream. */ >> + if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) { >> + tcg_out_insn(s, RR, BCR, >> + facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); >> + } > > args[0] == TCG_MO_ALL is always false since frontends bitwise-OR > TCG_BAR_SC. > > Did you mean: > > switch (args[0] & TCG_MO_ALL) { > case TCG_MO_ALL: /* fall-through */ > case TCG_MO_ST_LD: > tcg_out_insn(s, RR, BCR, > facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); > break; > } Yup, that is what is intended. It looks like this patch was fixed by rth when he merged it to do the correct thing. phew :) -- Pranith