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From: Pranith Kumar <bobby.prani@gmail.com>
Date: Wed, 1 Jun 2016 17:44:02 -0400
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Subject: Re: [Qemu-devel] [RFC v2 PATCH 02/13] tcg/i386: Add support for
 fence
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To: Richard Henderson <rth@twiddle.net>
Cc: "open list:i386 target" <qemu-devel@nongnu.org>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Sergey Fedorov <serge.fdrv@gmail.com>

On Wed, Jun 1, 2016 at 5:17 PM, Richard Henderson <rth@twiddle.net> wrote:
>
> Because x86 has a strong memory model.
>
> It does not require barriers to keep normal loads and stores in order.  The
> primary reason for the *fence instructions is to order the "non-temporal"
> memory operations that are part of the SSE instruction set, which we're not
> using at all.
>
> This is why you'll find
>
> /*
>  * Because of the strongly ordered storage model, wmb() and rmb() are nops
>  * here (a compiler barrier only).  QEMU doesn't do accesses to
> write-combining
>  * qemu memory or non-temporal load/stores from C code.
>  */
> #define smp_wmb()   barrier()
> #define smp_rmb()   barrier()
>
> for x86 and s390.


OK. For x86 target, that is true. I think I got the context confused.
On x86 target, we can elide the read and write barriers. But we still
need to generate 'mfence' to prevent store-after-load reordering. I
will refine this in the next version.

Thanks,
-- 
Pranith