From: Pranith Kumar <bobby.prani@gmail.com>
To: Richard Henderson <rth@twiddle.net>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches
Date: Tue, 5 Sep 2017 20:33:35 -0400 [thread overview]
Message-ID: <CAJhHMCBoOGrts1UvNVbC+g6fxLf_9MCYssNQ4nmqiTyzTLFXuQ@mail.gmail.com> (raw)
In-Reply-To: <efa7f1f6-af37-a06b-10b0-d40be2a502f0@twiddle.net>
On Tue, Sep 5, 2017 at 5:50 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 08/29/2017 10:23 AM, Pranith Kumar wrote:
>> This patch increases the number of entries cached in the TLB. I went
>> over a few architectures to see if increasing it is problematic. Only
>> armv6 seems to have a limitation that only 8 bits can be used for
>> indexing these entries. For other architectures, the number of TLB
>> entries is increased to a 4K-sized cache. The patch also doubles the
>> number of victim TLB entries.
>>
>> Some statistics collected from a build benchmark for various cache
>> sizes is listed below:
>>
>> | TLB bits\vTLB entires | 8 | 16 | 32 |
>> | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) |
>> | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
>> | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
>>
>> The best combination for this workload came out to be 12 bits for the
>> TLB and a 16 entry vTLB cache.
>
> This significantly degrades performance of alpha-softmmu.
> It spends about 25% of all cpu time in memset.
What workload does it degrade for? I will try to reproduce and see
which memset is causing this.
--
Pranith
next prev parent reply other threads:[~2017-09-06 0:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-29 17:23 [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches Pranith Kumar
2017-08-29 17:40 ` Richard Henderson
2017-09-05 21:50 ` Richard Henderson
2017-09-06 0:33 ` Pranith Kumar [this message]
2017-09-06 8:26 ` Richard Henderson
2017-09-06 8:55 ` Alex Bennée
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