From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB830CA9ED4 for ; Mon, 4 Nov 2019 21:29:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 873BC2084D for ; Mon, 4 Nov 2019 21:29:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PtstzIB3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729629AbfKDV3J (ORCPT ); Mon, 4 Nov 2019 16:29:09 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:50335 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728409AbfKDV3J (ORCPT ); Mon, 4 Nov 2019 16:29:09 -0500 Received: by mail-wm1-f66.google.com with SMTP id 11so18404540wmk.0; Mon, 04 Nov 2019 13:29:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Tp7E0KMvbL6BOAUu2NNrtQeKJbNH0Cxz/NvxU3jQlik=; b=PtstzIB3y4gOTVfBvLknyAu6/bRt6HO26iBUPi+jtjtcHKqtC3BAX5Vglcl36CTDXk vdyO63PGHx/jlldvBKhG8dxzO7elOem1o6UxjLObum4u9ajaoYO15TOxkzTfyi9+RJHj 8OQSze8CiegkGhAtfI3YvVvmgWMysT+QVDDuxjtgzHuQ4Puuj5RAelKdHfv8VvA95X/9 HEgwmpl6TybsMjv1V37wNav+xhxMHOHetk02mcJCJc12/4hedag2qv6OhSzyzep+xrjV aMz2z1v45p9bp93fv6GljUmPm9IfNkk8wxwViMJJJhPGskW53ydGxQTTzjsNzJljfi0G 3jrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Tp7E0KMvbL6BOAUu2NNrtQeKJbNH0Cxz/NvxU3jQlik=; b=bGqdcvmEEsuUex7IEna/S4sCp0IM6mLN652DaTIvVi5irxQCZV2ifWZS/WZfesxnUu l3h0MXQZaXvkLIOeC4wMq/6FyHV/6DOUC0Osqh9QRHkGUiB9ZW3+QMilCZPDfHzFM9+/ OKyibZHx7JkVIDi6g4Wf82aNXh2qCpiNkli3l79NUVXx5uobSu3zuSG/4Is51fym7Zqu Tl/GKB61zpf/7KFPBf5bHFHqJsI4ffNfHLUPJ26WsiZCtBblAFT0kFl6NK01ZvyfTUue mWgxaGiSXZuIXBNYTqPw8VAghrzt4b3fXnLmDGgKp4cm32y0LjwGfympaSSdmkRrT3D9 PmYA== X-Gm-Message-State: APjAAAXMWHR/NgWexXFAXFdBRloXWRpKS4ngvlFki6BJ4zkVTkb7kRso /abVpIhrVq3juctp7fjEXGQeBHp54zhRec8EozI= X-Google-Smtp-Source: APXvYqyn++80Z0P0IqvOwdBOky/MrB6MAOFkJrrpZmla4Vmh4glLP0MhXJPlaBoPF3H93AUZ23e4xWA86T3r+VljyWI= X-Received: by 2002:a05:600c:228e:: with SMTP id 14mr937906wmf.119.1572902945693; Mon, 04 Nov 2019 13:29:05 -0800 (PST) MIME-Version: 1.0 References: <20191103203334.10539-1-peron.clem@gmail.com> <20191103203334.10539-5-peron.clem@gmail.com> <20191104083835.m2pd4fvhn2ze6bjt@pengutronix.de> In-Reply-To: <20191104083835.m2pd4fvhn2ze6bjt@pengutronix.de> From: =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= Date: Mon, 4 Nov 2019 22:28:54 +0100 Message-ID: Subject: Re: [PATCH v2 4/7] pwm: sun4i: Add support to output source clock directly To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= Cc: Thierry Reding , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , linux-pwm@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , Jernej Skrabec Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Uwe On Mon, 4 Nov 2019 at 09:38, Uwe Kleine-K=C3=B6nig wrote: > > On Sun, Nov 03, 2019 at 09:33:31PM +0100, Cl=C3=A9ment P=C3=A9ron wrote: > > From: Jernej Skrabec > > > > PWM core has an option to bypass whole logic and output unchanged sourc= e > > clock as PWM output. This is achieved by enabling bypass bit. > > > > Note that when bypass is enabled, no other setting has any meaning, not > > even enable bit. > > > > This mode of operation is needed to achieve high enough frequency to > > serve as clock source for AC200 chip, which is integrated into same > > package as H6 SoC. > > I think the , should be dropped. > > > Signed-off-by: Jernej Skrabec > > Signed-off-by: Cl=C3=A9ment P=C3=A9ron > > --- > > drivers/pwm/pwm-sun4i.c | 39 ++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 38 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index b5e7ac364f59..2441574674d9 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -3,6 +3,10 @@ > > * Driver for Allwinner sun4i Pulse Width Modulation Controller > > * > > * Copyright (C) 2014 Alexandre Belloni > > + * > > + * Limitations: > > + * - When outputing the source clock directly, the PWM logic will be b= ypassed > > + * and the currently running period is not guaranted to be completed > > Typo: guaranted -> guaranteed > > > */ > > > > #include > > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] =3D { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_direct_mod_clk_output; > > unsigned int npwm; > > }; > > > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *c= hip, > > > > val =3D sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > + /* > > + * PWM chapter in H6 manual has a diagram which explains that if = bypass > > + * bit is set, no other setting has any meaning. Even more, exper= iment > > + * proved that also enable bit is ignored in this case. > > + */ > > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > > + data->has_direct_mod_clk_output) { > > + state->period =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk= _rate); > > + state->duty_cycle =3D state->period / 2; > > + state->polarity =3D PWM_POLARITY_NORMAL; > > + state->enabled =3D true; > > + return; > > + } > > Not sure how the rest of sun4i_pwm_get_state behaves, but I would prefer > to let .get_state() round up which together with .apply_state() rounding > down yields sound behaviour. Ok > > > + > > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) =3D=3D PWM_PRESCAL_MASK) && > > sun4i_pwm->data->has_prescaler_bypass) > > prescaler =3D 1; > > @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, s= truct pwm_device *pwm, > > { > > struct sun4i_pwm_chip *sun4i_pwm =3D to_sun4i_pwm_chip(chip); > > struct pwm_state cstate; > > - u32 ctrl; > > + u32 ctrl, clk_rate; > > + bool bypass; > > int ret; > > unsigned int delay_us; > > unsigned long now; > > @@ -218,6 +238,16 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, = struct pwm_device *pwm, > > } > > } > > > > + /* > > + * Although it would make much more sense to check for bypass in > > + * sun4i_pwm_calculate(), value of bypass bit also depends on "en= abled". > > + * Period is allowed to be rounded up or down. > > + */ > > + clk_rate =3D clk_get_rate(sun4i_pwm->clk); > > + bypass =3D ((state->period * clk_rate >=3D NSEC_PER_SEC && > > + state->period * clk_rate < NSEC_PER_SEC + clk_rate) && > > + state->enabled); > > I guess the compiler is smart enough here, but checking for > state->enabled is cheaper than the other checks, so putting this at the > start of the expression seems sensible. > > The comment doesn't match the code. You don't round up state->period. > (This is good, please fix the comment.) I think dropping the check > > state->period * clk_rate < NSEC_PER_SEC + clk_rate > > would be fine, too. Ok > > I'd like to have a check for > > state->duty_cycle * clk_rate >=3D NSEC_PER_SEC / 2 && > state->duty_cycle * clk_rate < NSEC_PER_SEC > > here. If this isn't true rather disable the PWM or output a 100% duty > cycle with a larger period. Why not just having the duty_cycle is 50% only ? state->duty_cycle * 2 =3D=3D state->period; Regards, Clement > > > + > > spin_lock(&sun4i_pwm->ctrl_lock); > > ctrl =3D sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-K=C3=B6nig = | > Industrial Linux Solutions | http://www.pengutronix.de/ = | From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1485CA9ED3 for ; Mon, 4 Nov 2019 21:29:11 +0000 (UTC) Received: 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<20191104083835.m2pd4fvhn2ze6bjt@pengutronix.de> From: =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= Date: Mon, 4 Nov 2019 22:28:54 +0100 Message-ID: Subject: Re: [PATCH v2 4/7] pwm: sun4i: Add support to output source clock directly To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191104_132907_956957_F140068A X-CRM114-Status: GOOD ( 31.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-pwm@vger.kernel.org, Jernej Skrabec , devicetree , linux-kernel , Maxime Ripard , Rob Herring , Chen-Yu Tsai , Thierry Reding , linux-arm-kernel Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org 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