From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EB5BC33C9E for ; Tue, 14 Jan 2020 16:52:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 436CE214AF for ; Tue, 14 Jan 2020 16:52:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PE93tZWV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728769AbgANQwz (ORCPT ); Tue, 14 Jan 2020 11:52:55 -0500 Received: from mail-io1-f67.google.com ([209.85.166.67]:40533 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726669AbgANQwz (ORCPT ); Tue, 14 Jan 2020 11:52:55 -0500 Received: by mail-io1-f67.google.com with SMTP id x1so14548273iop.7 for ; Tue, 14 Jan 2020 08:52:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=tvuqfPAmqeW5h6hFaCyRKpXD9b4Gjd3nwj+gcAvShZ0=; b=PE93tZWV+hg39DY1pUEJSq12EHHeocyMtfjbCr6ey/aNdjanGCOl24Wd3BFEcmEQet x8iyqIov7uNNXR1EI8XKsIR6DC8z8BpZIf2f4x55M6W21g94/Hmp1Hogt7ZOK3GXDqHv 09vied9075nNzXfQBJu47599bfeJMHVmsOLbs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=tvuqfPAmqeW5h6hFaCyRKpXD9b4Gjd3nwj+gcAvShZ0=; b=SaJnNkli6WgzL9oYnEom86NmLPIvpEBxQzVtMXNaKcDyw+M/ysrHGRzwMJZCNFy1SA oeZJsCOWRmFioAh1Ls7U2rnMLRQUyr/1tJC83h4BDBvrWxbE3RbTTAAll122nbCxqSCW 4qI4yNlEPEksqip80sIg4UfhR93rYqWlAgOkbPERedRjnOwEJkDIYiQCPj23wSxFAyvM q7JoWLK3Zmlmx9Upy5c4FDs2Hr24pkObOcWSMPdDCTPXB4CGRzbLM4j8G3ChaogLmdbE nNEriLPRA97Lwf/IJECydxLo+ZXDKpB3w1nW/KtG6gZXgr9raWsOxdC8nH9Qm5OmWZrW l7OA== X-Gm-Message-State: APjAAAXAoEB1GUhd3H97Ym1v2ip7BFqHIkqVCvLoBE9PsIONJnUEtBCp 5LYUQkwXx2xbpv8tTx+EJpXUT4+k9h0hXZnDt2UNcQ== X-Google-Smtp-Source: APXvYqxxSfCxs2zloh33teGyEGvf4zfmbUq0cbRO0d/xAKS5BgM2oPkXId2AZGiWDUDB+p8gcRw82UZWfTwiar2I8kc= X-Received: by 2002:a6b:6f06:: with SMTP id k6mr18407733ioc.204.1579020774522; Tue, 14 Jan 2020 08:52:54 -0800 (PST) MIME-Version: 1.0 References: <20200113153605.52350-1-brian@brkho.com> <20200113153605.52350-3-brian@brkho.com> <20200113175148.GC26711@jcrouse1-lnx.qualcomm.com> In-Reply-To: <20200113175148.GC26711@jcrouse1-lnx.qualcomm.com> From: Rob Clark Date: Tue, 14 Jan 2020 08:52:43 -0800 Message-ID: Subject: Re: [Freedreno] [PATCH 2/2] drm/msm: Add MSM_WAIT_IOVA ioctl To: Brian Ho , freedreno , Rob Clark , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Kristian Kristensen , Sean Paul Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote: > > On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote: > > + > > + vaddr = base_vaddr + args->offset; > > + > > + /* Assumes WC mapping */ > > + ret = wait_event_interruptible_timeout( > > + gpu->event, *vaddr >= args->value, remaining_jiffies); > > I feel like a barrier might be needed before checking *vaddr just in case you > get the interrupt and wake up the queue before the write posts from the > hardware. > if the gpu is doing posted (or cached) writes, I don't think there is even a CPU side barrier primitive that could wait for that? I think we rely on the GPU not interrupting the CPU until the write is posted BR, -R From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2F45C33CB1 for ; Wed, 15 Jan 2020 08:28:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72A8924683 for ; Wed, 15 Jan 2020 08:28:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PE93tZWV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 72A8924683 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AD4C6E88D; Wed, 15 Jan 2020 08:27:53 +0000 (UTC) Received: from mail-io1-xd42.google.com (mail-io1-xd42.google.com [IPv6:2607:f8b0:4864:20::d42]) by gabe.freedesktop.org (Postfix) with ESMTPS id 119A76E421 for ; Tue, 14 Jan 2020 16:52:55 +0000 (UTC) Received: by mail-io1-xd42.google.com with SMTP id i11so14549989ioi.12 for ; Tue, 14 Jan 2020 08:52:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=tvuqfPAmqeW5h6hFaCyRKpXD9b4Gjd3nwj+gcAvShZ0=; b=PE93tZWV+hg39DY1pUEJSq12EHHeocyMtfjbCr6ey/aNdjanGCOl24Wd3BFEcmEQet x8iyqIov7uNNXR1EI8XKsIR6DC8z8BpZIf2f4x55M6W21g94/Hmp1Hogt7ZOK3GXDqHv 09vied9075nNzXfQBJu47599bfeJMHVmsOLbs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=tvuqfPAmqeW5h6hFaCyRKpXD9b4Gjd3nwj+gcAvShZ0=; b=J09jRX+09jWF3ls0HDPEyykuCfWftblvMcc15732aBw9baFbNvv/hptv9iLFWM6U2B x8eBi1vWvy7fjuG+JFczzuE51kM8is2APBKPhCYYahY1Z4J5EkNVFw2n2v5iamAqzu42 ewQ2yNSy78idCKiRL4bV5q4f94Iq8DTFsh4HtOR4S70U6B8bojf4SgjgU3/svJ6Dmnkt ywUcSndFiAP1tx6V9AuDztzZqlYJbf8fOGvX0Wcb+xylekZdAoJuOOU9o6cU6L1h/sSj DJT6mMoeJp8feMHZytxQuPQWYO0JurUCkcAYXM9rk0bn6ej6lfyS4Z2Ieu66BN1hk4U9 jRgQ== X-Gm-Message-State: APjAAAXyh8ftgiytkQPa6WyVuE97Fvf5FwiZN94BR23cW0I3KGVvtyeH 74yS6EqsqhOBF7p7+cg07wKggHrv2U3x8JNbi+G23Q== X-Google-Smtp-Source: APXvYqxxSfCxs2zloh33teGyEGvf4zfmbUq0cbRO0d/xAKS5BgM2oPkXId2AZGiWDUDB+p8gcRw82UZWfTwiar2I8kc= X-Received: by 2002:a6b:6f06:: with SMTP id k6mr18407733ioc.204.1579020774522; Tue, 14 Jan 2020 08:52:54 -0800 (PST) MIME-Version: 1.0 References: <20200113153605.52350-1-brian@brkho.com> <20200113153605.52350-3-brian@brkho.com> <20200113175148.GC26711@jcrouse1-lnx.qualcomm.com> In-Reply-To: <20200113175148.GC26711@jcrouse1-lnx.qualcomm.com> From: Rob Clark Date: Tue, 14 Jan 2020 08:52:43 -0800 Message-ID: Subject: Re: [Freedreno] [PATCH 2/2] drm/msm: Add MSM_WAIT_IOVA ioctl To: Brian Ho , freedreno , Rob Clark , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Kristian Kristensen , Sean Paul X-Mailman-Approved-At: Wed, 15 Jan 2020 08:27:50 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote: > > On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote: > > + > > + vaddr = base_vaddr + args->offset; > > + > > + /* Assumes WC mapping */ > > + ret = wait_event_interruptible_timeout( > > + gpu->event, *vaddr >= args->value, remaining_jiffies); > > I feel like a barrier might be needed before checking *vaddr just in case you > get the interrupt and wake up the queue before the write posts from the > hardware. > if the gpu is doing posted (or cached) writes, I don't think there is even a CPU side barrier primitive that could wait for that? I think we rely on the GPU not interrupting the CPU until the write is posted BR, -R _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel