From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Edgar E. Iglesias" Subject: Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC Date: Wed, 11 Mar 2015 20:09:06 +1000 Message-ID: References: <1425955798-7530-1-git-send-email-edgar.iglesias@gmail.com> <54FED5C2.50903@linaro.org> <20150310235942.GA16866@toto> <1426067199.21353.143.camel@citrix.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0420528296057476101==" Return-path: In-Reply-To: <1426067199.21353.143.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org --===============0420528296057476101== Content-Type: multipart/alternative; boundary=90e6ba6147e220ac7505110075ca --90e6ba6147e220ac7505110075ca Content-Type: text/plain; charset=UTF-8 Sorry for top post. That makes sense, thanks! Cheers, Edgar --- Sent from my phone On 11/03/2015 7:46 pm, "Ian Campbell" wrote: > On Wed, 2015-03-11 at 09:59 +1000, Edgar E. Iglesias wrote: > > On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote: > > > Hello Edgar, > > > > > > Thank you for adding support of the ZynqMP. > > > > > > On 10/03/15 02:49, Edgar E. Iglesias wrote: > > > > From: "Edgar E. Iglesias" > > > > > > > > Adds support for the Cadence UART in Xilinx ZynqMP. The > > > > rest of the ZynqMP platform is discovered via device-tree. > > > > > > Did you make sure that the default grant table range (0xb0000000 - > > > 0xb0020000) don't overlap with an hardware region? > > > > No I didn't, thanks for pointing that out. I need to move these to > > another address. > > > > So now I'm back to needing platform specific code. Long term, > > Maybe it would make sense making the grant table range somehow > > configurable via DT? > > The plan is to have Xen preallocate the grant table pages and expose > their physical address to dom0, so when dom0 then maps it 1:1 it won't > clash with either memory used by Xen or by the dom0's actual assigned > memory and since it is RAM it can't possibly clash with any MMIO. > > > Anyway, I'll send a v4 with the platform code to move the gnt > > into a reserved area in the memory map. > > Ian. > > --90e6ba6147e220ac7505110075ca Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

Sorry for top post.

That makes sense, thanks!

Cheers,
Edgar

---
Sent from my phone

On 11/03/2015 7:46 pm, "Ian Campbell" = <ian.campbell@citrix.com&= gt; wrote:
On Wed, = 2015-03-11 at 09:59 +1000, Edgar E. Iglesias wrote:
> On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote:
> > Hello Edgar,
> >
> > Thank you for adding support of the ZynqMP.
> >
> > On 10/03/15 02:49, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > >
> > > Adds support for the Cadence UART in Xilinx ZynqMP. The
> > > rest of the ZynqMP platform is discovered via device-tree. > >
> > Did you make sure that the default grant table range (0xb0000000 = -
> > 0xb0020000) don't overlap with an hardware region?
>
> No I didn't, thanks for pointing that out. I need to move these to=
> another address.
>
> So now I'm back to needing platform specific code. Long term,
> Maybe it would make sense making the grant table range somehow
> configurable via DT?

The plan is to have Xen preallocate the grant table pages and expose
their physical address to dom0, so when dom0 then maps it 1:1 it won't<= br> clash with either memory used by Xen or by the dom0's actual assigned memory and since it is RAM it can't possibly clash with any MMIO.

> Anyway, I'll send a v4 with the platform code to move the gnt
> into a reserved area in the memory map.

Ian.

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