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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Sergey Fedorov" <serge.fdrv@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Alexander Graf" <agraf@suse.de>,
	"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v5 4/6] target-arm: Add the Hypervisor timer
Date: Fri, 10 Jul 2015 21:30:59 +1000	[thread overview]
Message-ID: <CAJy5ezqoaCY=4D+qMW91k6OBzk-cYYiS027YjBR5bMEG0AJ2Bg@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA8FjAFQOvr4ZhgzVY0QFsSb-4WdLgoE-LXkN6++KiLm7g@mail.gmail.com>

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On 10/07/2015 9:26 pm, "Peter Maydell" <peter.maydell@linaro.org> wrote:
>
> On 10 July 2015 at 12:23, Edgar E. Iglesias <edgar.iglesias@gmail.com>
wrote:
> >
> > On 10/07/2015 7:58 pm, "Peter Maydell" <peter.maydell@linaro.org> wrote:
> >> Something I just noticed while I was trying to add support
> >> for the secure physical timer on top of this series: the
> >> gt_*_cnt_reset functions are misnamed, because they're not
> >> resetting the counters, they're resetting the timers.
> >> (There are only two counters, physical and virtual, but there
> >> are four timers, physical, secure-physical, virtual and hyp.
> >> Since our reset function is deleting the underlying QEMU
> >> timer it's a timer reset, not a counter reset.)
> >> We should probably fix up the names and make sure they're
> >> associated with the correct registers (the phys and virt
> >> timer reset is currently hanging off a counter register)
>
> > Hi, yes that sounds good. Btw are you fixing this as you go or should I
send
> > a new series fixing your comments? I've fixed the stuff you commented
on a
> > few days ago in my tree...
>
> I rebased as I was reviewing it and am currently basing my
> secure-timer patches on that. It would probably be good if
> you fixed up the naming issue here and resent, and then I'll
> rebase on top of that.
>
> -- PMM

Ok, sounds good.

Cheers,
Edgar

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  reply	other threads:[~2015-07-10 11:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-16  1:51 [Qemu-devel] [PATCH v5 0/6] arm: Steps towards EL2 support round 3 Edgar E. Iglesias
2015-06-16  1:51 ` [Qemu-devel] [PATCH v5 1/6] target-arm: Add CNTVOFF_EL2 Edgar E. Iglesias
2015-07-07 13:55   ` Peter Maydell
2015-06-16  1:51 ` [Qemu-devel] [PATCH v5 2/6] target-arm: Add CNTHCTL_EL2 Edgar E. Iglesias
2015-07-07 13:55   ` Peter Maydell
2015-06-16  1:51 ` [Qemu-devel] [PATCH v5 3/6] target-arm: Pass timeridx as argument to various timer functions Edgar E. Iglesias
2015-06-16  1:51 ` [Qemu-devel] [PATCH v5 4/6] target-arm: Add the Hypervisor timer Edgar E. Iglesias
2015-07-07 14:01   ` Peter Maydell
2015-07-10  9:58   ` Peter Maydell
2015-07-10 11:23     ` Edgar E. Iglesias
2015-07-10 11:25       ` Peter Maydell
2015-07-10 11:30         ` Edgar E. Iglesias [this message]
2015-07-13 13:12         ` Edgar E. Iglesias
2015-06-16  1:51 ` [Qemu-devel] [PATCH v5 5/6] hw/arm/virt: Replace magic IRQ constants with macros Edgar E. Iglesias
2015-06-16  1:51 ` [Qemu-devel] [PATCH v5 6/6] hw/arm/virt: Connect the Hypervisor timer Edgar E. Iglesias
2015-06-18 16:27 ` [Qemu-devel] [PATCH v5 0/6] arm: Steps towards EL2 support round 3 Peter Maydell
2015-06-18 16:59   ` Edgar E. Iglesias

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