From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B91CDC432C0 for ; Tue, 26 Nov 2019 20:43:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CFA520862 for ; Tue, 26 Nov 2019 20:43:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dOpabZbf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CFA520862 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:58892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZhgP-0007fr-GR for qemu-devel@archiver.kernel.org; Tue, 26 Nov 2019 15:43:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43953) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZheb-0006nX-Ve for qemu-devel@nongnu.org; Tue, 26 Nov 2019 15:41:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZheZ-0007mE-ND for qemu-devel@nongnu.org; Tue, 26 Nov 2019 15:41:45 -0500 Received: from mail-qt1-x842.google.com ([2607:f8b0:4864:20::842]:33958) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iZheZ-0007lG-HD for qemu-devel@nongnu.org; Tue, 26 Nov 2019 15:41:43 -0500 Received: by mail-qt1-x842.google.com with SMTP id i17so22943089qtq.1 for ; Tue, 26 Nov 2019 12:41:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=gBAMQHPt91TGMLvQK37duKjPHEWnakH+78TgrySypUM=; b=dOpabZbf/DVqNswwGM0ALIaxvXm77fl0RJk4tqB7kqXMLkyF9nSs+dX+7l0bEe0M/K 4+O1OIfaMy6CpKOI+UC3rBUXWfYZ6sVkXB3AB+ea49ILXNcsc7Z7vgaeOK0oHIFc0gET fvmQSwypEZFgTmz8253Sx1Ho9M/gmnYTZbunPlb36j45cDi4R0SSBbcZF540QJuhuUQp lGewjY9UqSUoEUaGjgW8CGwBDyTRRZP/SrjEa3gSnbbtNYLVg94lug2/1FcmBaJpVzcx m3wEPtjJcQS7DHo1KeBnucunmF0u6bqWHZCEBJuaXXCqj+qOAJCE0upXSWtMHEt00VPt U2Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gBAMQHPt91TGMLvQK37duKjPHEWnakH+78TgrySypUM=; b=WyIOJ0mcyXjlflyrVGZrDE3jtX07kjRrlx+vuC1Q68AW04uJckp+P4Aflcny/9zb3N s60HnC5XulzqjBp0De4Z+CfSI9L2YQNTI0ri9zBKgz1XI38Ok+S7G2k6Ahn6BpS1YDBe ZC4if8v6vhjT869955/i3AVA6nyY2dfWFRSUWWPtUM08yUUAp6Xt2vlRiN+qUya2i2Og otSNfk17RNV1D+JVSdFqCjFwIvPhHV5A24KHRIrynl4itLPEuJnjwWLXciDpzViPFlBm mzA0T53iv4iPzwXoxIfDgebChi1R8w6m/ibmMcBprRGi2Ji4ZvxoErN6So8R5BNJYhEN 6nIQ== X-Gm-Message-State: APjAAAW4cDfVNyP4sRte2Vagq+g1Jt/HWBod6gQFCDSayV93BwUCgcAv qsCcFefNLlAtPqZ+VW+ZVOODfTnrKfjEHW9pU2k= X-Google-Smtp-Source: APXvYqz06BwmF/tJxRMtL11fW4rvm/mTic0J9W74vjTaVRg9+mtUmr1xyMKgwVbULP+WgLashFJW0BBN73ka+c4C/Yk= X-Received: by 2002:ac8:5516:: with SMTP id j22mr3513332qtq.160.1574800902508; Tue, 26 Nov 2019 12:41:42 -0800 (PST) MIME-Version: 1.0 References: <20191124050225.30351-1-mrolnik@gmail.com> <20191124050225.30351-5-mrolnik@gmail.com> In-Reply-To: From: Michael Rolnik Date: Tue, 26 Nov 2019 22:40:35 +0200 Message-ID: Subject: Re: [PATCH v36 04/17] target/avr: Add instruction translation - Registers definition To: Aleksandar Markovic Content-Type: multipart/alternative; boundary="00000000000062d6ef059845e89f" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::842 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Richard Henderson , QEMU Developers , Pavel Dovgalyuk , Igor Mammedov , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000062d6ef059845e89f Content-Type: text/plain; charset="UTF-8" On Tue, Nov 26, 2019 at 9:48 PM Aleksandar Markovic < aleksandar.m.mail@gmail.com> wrote: > On Sun, Nov 24, 2019 at 6:03 AM Michael Rolnik wrote: > > > > Signed-off-by: Michael Rolnik > > --- > > target/avr/translate.c | 132 +++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 132 insertions(+) > > create mode 100644 target/avr/translate.c > > > > diff --git a/target/avr/translate.c b/target/avr/translate.c > > new file mode 100644 > > index 0000000000..53c9892a60 > > --- /dev/null > > +++ b/target/avr/translate.c > > @@ -0,0 +1,132 @@ > > +/* > > + * QEMU AVR CPU > > + * > > + * Copyright (c) 2019 Michael Rolnik > > + * > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see > > + * > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/qemu-print.h" > > +#include "tcg/tcg.h" > > +#include "cpu.h" > > +#include "exec/exec-all.h" > > +#include "disas/disas.h" > > +#include "tcg-op.h" > > +#include "exec/cpu_ldst.h" > > +#include "exec/helper-proto.h" > > +#include "exec/helper-gen.h" > > +#include "exec/log.h" > > +#include "exec/gdbstub.h" > > +#include "exec/translator.h" > > +#include "exec/gen-icount.h" > > + > > +/* > > + * Define if you want a BREAK instruction translated to a breakpoint > > + * Active debugging connection is assumed > > + * This is for > > + * > https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests > > + * tests > > + */ > > +#undef BREAKPOINT_ON_BREAK > > + > > +static TCGv cpu_pc; > > + > > +static TCGv cpu_Cf; > > +static TCGv cpu_Zf; > > +static TCGv cpu_Nf; > > +static TCGv cpu_Vf; > > +static TCGv cpu_Sf; > > +static TCGv cpu_Hf; > > +static TCGv cpu_Tf; > > +static TCGv cpu_If; > > + > > +static TCGv cpu_rampD; > > +static TCGv cpu_rampX; > > +static TCGv cpu_rampY; > > +static TCGv cpu_rampZ; > > + > > +static TCGv cpu_r[NO_CPU_REGISTERS]; > > +static TCGv cpu_eind; > > +static TCGv cpu_sp; > > + > > +static TCGv cpu_skip; > > + > > +static const char reg_names[NO_CPU_REGISTERS][8] = { > > + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", > > + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", > > + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", > > + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", > > +}; > > +#define REG(x) (cpu_r[x]) > > + > > +enum { > > + DISAS_EXIT = DISAS_TARGET_0, /* We want return to the cpu main > loop. */ > > + DISAS_LOOKUP = DISAS_TARGET_1, /* We have a variable condition > exit. */ > > + DISAS_CHAIN = DISAS_TARGET_2, /* We have a single condition > exit. */ > > +}; > > + > > +typedef struct DisasContext DisasContext; > > + > > +/* This is the state at translation time. */ > > +struct DisasContext { > > + TranslationBlock *tb; > > + > > + CPUAVRState *env; > > + CPUState *cs; > > + > > + target_long npc; > > + uint32_t opcode; > > + > > + /* Routine used to access memory */ > > + int memidx; > > + int bstate; > > + int singlestep; > > + > > + TCGv skip_var0; > > + TCGv skip_var1; > > + TCGCond skip_cond; > > + bool free_skip_var0; > > This set of four lines are by far the hardest to connect to the > documentation. > > Please add before them a sizable comment with explanations for: > > - the reson these variables are introduced > - why are they here (part of DisasContext) > - what they affect > - summary of the way they work > > Perhaps add comments to other places where "skip"-related data fields > are introduced. > > (I believe the implementation is correct, but it is extremely hard to the > reader > to reverse-engineer the intentions) > > Yours, > Aleksandar > Aleksandar, My original implementation was different. This piece of code belongs to Richard (he also listed as a co developer). so, if Richard has time, I prefer him to answer otherwise I will try to explain myself. Regards, Michael > > > +}; > > + > > +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); > } > > +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); } > > +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * > 2; } > > +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; } > > + > > +static uint16_t next_word(DisasContext *ctx) > > +{ > > + return cpu_lduw_code(ctx->env, ctx->npc++ * 2); > > +} > > + > > +static int append_16(DisasContext *ctx, int x) > > +{ > > + return x << 16 | next_word(ctx); > > +} > > + > > + > > +static bool avr_have_feature(DisasContext *ctx, int feature) > > +{ > > + if (!avr_feature(ctx->env, feature)) { > > + gen_helper_unsupported(cpu_env); > > + ctx->bstate = DISAS_NORETURN; > > + return false; > > + } > > + return true; > > +} > > + > > +static bool decode_insn(DisasContext *ctx, uint16_t insn); > > +#include "decode_insn.inc.c" > > + > > -- > > 2.17.2 (Apple Git-113) > > > -- Best Regards, Michael Rolnik --00000000000062d6ef059845e89f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Nov 26, 2019 at 9:48 PM Aleks= andar Markovic <aleksanda= r.m.mail@gmail.com> wrote:
On Sun, Nov 24, 2019 at 6:03 AM Michael Rolnik <mrolnik@gmail.com> = wrote:
>
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> ---
>=C2=A0 target/avr/translate.c | 132 +++++++++++++++++++++++++++++++++++= ++++++
>=C2=A0 1 file changed, 132 insertions(+)
>=C2=A0 create mode 100644 target/avr/translate.c
>
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> new file mode 100644
> index 0000000000..53c9892a60
> --- /dev/null
> +++ b/target/avr/translate.c
> @@ -0,0 +1,132 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.=
> + *
> + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the= GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html&= gt;
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/qemu-print.h"
> +#include "tcg/tcg.h"
> +#include "cpu.h"
> +#include "exec/exec-all.h"
> +#include "disas/disas.h"
> +#include "tcg-op.h"
> +#include "exec/cpu_ldst.h"
> +#include "exec/helper-proto.h"
> +#include "exec/helper-gen.h"
> +#include "exec/log.h"
> +#include "exec/gdbstub.h"
> +#include "exec/translator.h"
> +#include "exec/gen-icount.h"
> +
> +/*
> + *=C2=A0 Define if you want a BREAK instruction translated to a break= point
> + *=C2=A0 Active debugging connection is assumed
> + *=C2=A0 This is for
> + *=C2=A0 https://githu= b.com/seharris/qemu-avr-tests/tree/master/instruction-tests
> + *=C2=A0 tests
> + */
> +#undef BREAKPOINT_ON_BREAK
> +
> +static TCGv cpu_pc;
> +
> +static TCGv cpu_Cf;
> +static TCGv cpu_Zf;
> +static TCGv cpu_Nf;
> +static TCGv cpu_Vf;
> +static TCGv cpu_Sf;
> +static TCGv cpu_Hf;
> +static TCGv cpu_Tf;
> +static TCGv cpu_If;
> +
> +static TCGv cpu_rampD;
> +static TCGv cpu_rampX;
> +static TCGv cpu_rampY;
> +static TCGv cpu_rampZ;
> +
> +static TCGv cpu_r[NO_CPU_REGISTERS];
> +static TCGv cpu_eind;
> +static TCGv cpu_sp;
> +
> +static TCGv cpu_skip;
> +
> +static const char reg_names[NO_CPU_REGISTERS][8] =3D {
> +=C2=A0 =C2=A0 "r0",=C2=A0 "r1",=C2=A0 "r2&qu= ot;,=C2=A0 "r3",=C2=A0 "r4",=C2=A0 "r5",=C2= =A0 "r6",=C2=A0 "r7",
> +=C2=A0 =C2=A0 "r8",=C2=A0 "r9",=C2=A0 "r10&q= uot;, "r11", "r12", "r13", "r14", &= quot;r15",
> +=C2=A0 =C2=A0 "r16", "r17", "r18", &quo= t;r19", "r20", "r21", "r22", "r23&q= uot;,
> +=C2=A0 =C2=A0 "r24", "r25", "r26", &quo= t;r27", "r28", "r29", "r30", "r31&q= uot;,
> +};
> +#define REG(x) (cpu_r[x])
> +
> +enum {
> +=C2=A0 =C2=A0 DISAS_EXIT=C2=A0 =C2=A0=3D DISAS_TARGET_0,=C2=A0 /* We = want return to the cpu main loop.=C2=A0 */
> +=C2=A0 =C2=A0 DISAS_LOOKUP =3D DISAS_TARGET_1,=C2=A0 /* We have a var= iable condition exit.=C2=A0 */
> +=C2=A0 =C2=A0 DISAS_CHAIN=C2=A0 =3D DISAS_TARGET_2,=C2=A0 /* We have = a single condition exit.=C2=A0 */
> +};
> +
> +typedef struct DisasContext DisasContext;
> +
> +/* This is the state at translation time. */
> +struct DisasContext {
> +=C2=A0 =C2=A0 TranslationBlock *tb;
> +
> +=C2=A0 =C2=A0 CPUAVRState *env;
> +=C2=A0 =C2=A0 CPUState *cs;
> +
> +=C2=A0 =C2=A0 target_long npc;
> +=C2=A0 =C2=A0 uint32_t opcode;
> +
> +=C2=A0 =C2=A0 /* Routine used to access memory */
> +=C2=A0 =C2=A0 int memidx;
> +=C2=A0 =C2=A0 int bstate;
> +=C2=A0 =C2=A0 int singlestep;
> +
> +=C2=A0 =C2=A0 TCGv skip_var0;
> +=C2=A0 =C2=A0 TCGv skip_var1;
> +=C2=A0 =C2=A0 TCGCond skip_cond;
> +=C2=A0 =C2=A0 bool free_skip_var0;

This set of four lines are by far the hardest to connect to the documentati= on.

Please add before them a sizable comment with explanations for:

- the reson these variables are introduced
- why are they here (part of DisasContext)
- what they affect
- summary of the way they work

Perhaps add comments to other places where "skip"-related data fi= elds
are introduced.

(I believe the implementation is correct, but it is extremely hard to the r= eader
to reverse-engineer the intentions)

Yours,
Aleksandar

Aleksandar,

My original implementation was different. This piece of code belon= gs to Richard (he also listed as a co developer). so, if Richard has time, = I prefer him to answer otherwise I will try to explain myself.
Regards,
Michael=C2=A0

> +};
> +
> +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16= ); }
> +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8)= ; }
> +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4)= * 2; }
> +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2= ; }
> +
> +static uint16_t next_word(DisasContext *ctx)
> +{
> +=C2=A0 =C2=A0 return cpu_lduw_code(ctx->env, ctx->npc++ * 2); > +}
> +
> +static int append_16(DisasContext *ctx, int x)
> +{
> +=C2=A0 =C2=A0 return x << 16 | next_word(ctx);
> +}
> +
> +
> +static bool avr_have_feature(DisasContext *ctx, int feature)
> +{
> +=C2=A0 =C2=A0 if (!avr_feature(ctx->env, feature)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_helper_unsupported(cpu_env);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ctx->bstate =3D DISAS_NORETURN;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 return true;
> +}
> +
> +static bool decode_insn(DisasContext *ctx, uint16_t insn);
> +#include "decode_insn.inc.c"
> +
> --
> 2.17.2 (Apple Git-113)
>


--
Best Regards,
Michael Rolnik
--00000000000062d6ef059845e89f--