From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D78C43603 for ; Thu, 5 Dec 2019 13:49:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 241F12464D for ; Thu, 5 Dec 2019 13:49:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lzZ8zk2s" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 241F12464D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54357 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icrVK-0000au-7N for qemu-devel@archiver.kernel.org; Thu, 05 Dec 2019 08:49:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47121) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icrKG-0006vq-IA for qemu-devel@nongnu.org; Thu, 05 Dec 2019 08:37:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icrJz-00034v-Ip for qemu-devel@nongnu.org; Thu, 05 Dec 2019 08:37:41 -0500 Received: from mail-vk1-xa41.google.com ([2607:f8b0:4864:20::a41]:46260) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icrJz-0002zq-5a for qemu-devel@nongnu.org; Thu, 05 Dec 2019 08:37:31 -0500 Received: by mail-vk1-xa41.google.com with SMTP id u6so1081759vkn.13 for ; Thu, 05 Dec 2019 05:37:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Svy9Frf3+iiJZXLruZmdVgShBae5icU+Mw5+TU3oMgU=; b=lzZ8zk2sTK+bPuXTha2biXo+30egCHF7URkqeHeJKGX82FtytXw3TOZ2a5HsNuweUl iM/pjaz2vDQ2iWvy087peRkbPJ8X957hrmJf4zjWPEFpMuFwu9jO9sGC0zK5ivGA8dHB qLvNSMKZ1PHW5elS0Rsm637PSm0cKWef1KIAixtxbRrbPTveQ2SXexi8+f7GejfWrXfS BI+/5SB16QdBgTBZH+XTFsrm6BwXhzwi80m52lCauwiFnNh1+48nra5x3srMaRYYwG+z VZcB7BgVg4Ul9bGkeW265d9JCSsJQdxwH+HFDcB7uZnkNNwlcrJyHnT1vG4sbqnH0PrE jSrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Svy9Frf3+iiJZXLruZmdVgShBae5icU+Mw5+TU3oMgU=; b=qtUhXI6UDcV1HAwm8V41IQJ24e4qHcJ+8lhdeCOnb0jnlpv0IQQg035ofeBYCeVaJb CcPcvn5MvxvL59d/HREfslQC8IW6F5Er1b8TyLkENJD5VUOmhCQD9+/nCH4lQTcJF3it jz7toKlDB8dfUUSVvxu1bHhDnTDgmTN9WmUSLu+wLqGxo8RDyTU3sb+ncl5StFI/YXRp LT+JfE52tC4if8w37YUuGsd/FV4SoDwg7QdLdReWczKb+Ngu0UGNPXWOddV3/rumCPbR sQElJts6ntC7r3ox6RnPFKlC5qo1oIg+NrG11SP0XYPhGWz2/LKj/6zM4RDjTdop28j/ sUmw== X-Gm-Message-State: APjAAAUwj33/TEF2SrOui5mfpa0sjYbfVIO+++QqQKwfQa9/XpZfCD5w nTY3QzyY00tBWubcqvGmXNkW0K+VXEDFHwoCd+lwmQmV4BSy2A== X-Google-Smtp-Source: APXvYqxIi9icXzsPs24aHI+CKUuFdBiW/7ivTRZjiHlb2msUqLPjp50gtr2yaSu801sDuthOWKAlyos4k4fg6NXOsLM= X-Received: by 2002:a0c:e9cf:: with SMTP id q15mr7332785qvo.137.1575552571915; Thu, 05 Dec 2019 05:29:31 -0800 (PST) MIME-Version: 1.0 References: <20191127175257.23480-1-mrolnik@gmail.com> <20191127175257.23480-8-mrolnik@gmail.com> In-Reply-To: From: Michael Rolnik Date: Thu, 5 Dec 2019 15:28:53 +0200 Message-ID: Subject: Re: [PATCH v37 07/17] target/avr: Add instruction translation - Bit and Bit-test Instructions To: Aleksandar Markovic Content-Type: multipart/alternative; boundary="0000000000005fc2ac0598f4eb78" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::a41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "thuth@redhat.com" , "me@xcancerberox.com.ar" , "richard.henderson@linaro.org" , "qemu-devel@nongnu.org" , "dovgaluk@ispras.ru" , "imammedo@redhat.com" , "philmd@redhat.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000005fc2ac0598f4eb78 Content-Type: text/plain; charset="UTF-8" my mistake. Thanks. I will split it. On Thu, Dec 5, 2019 at 3:17 PM Michael Rolnik wrote: > I think they do follow the division in the docs. > > On Thu, Dec 5, 2019 at 2:28 PM Aleksandar Markovic < > aleksandar.m.mail@gmail.com> wrote: > >> >> >> On Wednesday, November 27, 2019, Michael Rolnik >> wrote: >> >>> This includes: >>> - LSR, ROR >>> - ASR >>> - SWAP >>> - SBI, CBI >>> - BST, BLD >>> - BSET, BCLR >>> >>> Signed-off-by: Michael Rolnik >>> --- >>> target/avr/translate.c | 1123 ++++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 1123 insertions(+) >>> >>> >> Hello, Michael >> >> I said I am on vacation, and truly I am, but, fir the next version if the >> series, I would like to ask you to extract "data transfer" instruction (as >> defined in avr docs, MOV LD ST etc) from this patch, and create a new patch >> for them - so that the patches follow the division from docs. >> >> Yours, >> Aleksandar >> >> >> >> >> >>> diff --git a/target/avr/translate.c b/target/avr/translate.c >>> index 48a42c984a..dc6a1af2fc 100644 >>> --- a/target/avr/translate.c >>> +++ b/target/avr/translate.c >>> @@ -317,6 +317,15 @@ static void gen_goto_tb(DisasContext *ctx, int n, >>> target_ulong dest) >>> } >>> >>> >>> +static void gen_rshift_ZNVSf(TCGv R) >>> +{ >>> + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ >>> + tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ >>> + tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf); >>> + tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ >>> +} >>> + >>> + >>> /* >>> * Adds two registers without the C Flag and places the result in the >>> * destination register Rd. >>> @@ -1508,3 +1517,1117 @@ static bool trans_BRBS(DisasContext *ctx, >>> arg_BRBS *a) >>> return true; >>> } >>> >>> + >>> +/* >>> + * This instruction makes a copy of one register into another. The >>> source >>> + * register Rr is left unchanged, while the destination register Rd is >>> loaded >>> + * with a copy of Rr. >>> + */ >>> +static bool trans_MOV(DisasContext *ctx, arg_MOV *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv Rr = cpu_r[a->rr]; >>> + >>> + tcg_gen_mov_tl(Rd, Rr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * This instruction makes a copy of one register pair into another >>> register >>> + * pair. The source register pair Rr+1:Rr is left unchanged, while the >>> + * destination register pair Rd+1:Rd is loaded with a copy of Rr + >>> 1:Rr. This >>> + * instruction is not available in all devices. Refer to the device >>> specific >>> + * instruction set summary. >>> + */ >>> +static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) { >>> + return true; >>> + } >>> + >>> + TCGv RdL = cpu_r[a->rd]; >>> + TCGv RdH = cpu_r[a->rd + 1]; >>> + TCGv RrL = cpu_r[a->rr]; >>> + TCGv RrH = cpu_r[a->rr + 1]; >>> + >>> + tcg_gen_mov_tl(RdH, RrH); >>> + tcg_gen_mov_tl(RdL, RrL); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads an 8 bit constant directly to register 16 to 31. >>> + */ >>> +static bool trans_LDI(DisasContext *ctx, arg_LDI *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + int imm = a->imm; >>> + >>> + tcg_gen_movi_tl(Rd, imm); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads one byte from the data space to a register. For parts with >>> SRAM, >>> + * the data space consists of the Register File, I/O memory and >>> internal SRAM >>> + * (and external SRAM if applicable). For parts without SRAM, the data >>> space >>> + * consists of the register file only. The EEPROM has a separate >>> address space. >>> + * A 16-bit address must be supplied. Memory access is limited to the >>> current >>> + * data segment of 64KB. The LDS instruction uses the RAMPD Register >>> to access >>> + * memory above 64KB. To access another data segment in devices with >>> more than >>> + * 64KB data space, the RAMPD in register in the I/O area has to be >>> changed. >>> + * This instruction is not available in all devices. Refer to the >>> device >>> + * specific instruction set summary. >>> + */ >>> +static bool trans_LDS(DisasContext *ctx, arg_LDS *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = tcg_temp_new_i32(); >>> + TCGv H = cpu_rampD; >>> + a->imm = next_word(ctx); >>> + >>> + tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ >>> + tcg_gen_shli_tl(addr, addr, 16); >>> + tcg_gen_ori_tl(addr, addr, a->imm); >>> + >>> + gen_data_load(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads one byte indirect from the data space to a register. For parts >>> + * with SRAM, the data space consists of the Register File, I/O memory >>> and >>> + * internal SRAM (and external SRAM if applicable). For parts without >>> SRAM, the >>> + * data space consists of the Register File only. In some parts the >>> Flash >>> + * Memory has been mapped to the data space and can be read using this >>> command. >>> + * The EEPROM has a separate address space. The data location is >>> pointed to by >>> + * the X (16 bits) Pointer Register in the Register File. Memory >>> access is >>> + * limited to the current data segment of 64KB. To access another data >>> segment >>> + * in devices with more than 64KB data space, the RAMPX in register in >>> the I/O >>> + * area has to be changed. The X-pointer Register can either be left >>> unchanged >>> + * by the operation, or it can be post-incremented or predecremented. >>> These >>> + * features are especially suited for accessing arrays, tables, and >>> Stack >>> + * Pointer usage of the X-pointer Register. Note that only the low >>> byte of the >>> + * X-pointer is updated in devices with no more than 256 bytes data >>> space. For >>> + * such devices, the high byte of the pointer is not used by this >>> instruction >>> + * and can be used for other purposes. The RAMPX Register in the I/O >>> area is >>> + * updated in parts with more than 64KB data space or more than 64KB >>> Program >>> + * memory, and the increment/decrement is added to the entire 24-bit >>> address on >>> + * such devices. Not all variants of this instruction is available in >>> all >>> + * devices. Refer to the device specific instruction set summary. In >>> the >>> + * Reduced Core tinyAVR the LD instruction can be used to achieve the >>> same >>> + * operation as LPM since the program memory is mapped to the data >>> memory >>> + * space. >>> + */ >>> +static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_xaddr(); >>> + >>> + gen_data_load(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_xaddr(); >>> + >>> + gen_data_load(ctx, Rd, addr); >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + >>> + gen_set_xaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_xaddr(); >>> + >>> + tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ >>> + gen_data_load(ctx, Rd, addr); >>> + gen_set_xaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STX1(DisasContext *ctx, arg_STX1 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rr]; >>> + TCGv addr = gen_get_xaddr(); >>> + >>> + gen_data_store(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> +static bool trans_STX2(DisasContext *ctx, arg_STX2 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rr]; >>> + TCGv addr = gen_get_xaddr(); >>> + >>> + gen_data_store(ctx, Rd, addr); >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + gen_set_xaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> +static bool trans_STX3(DisasContext *ctx, arg_STX3 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rr]; >>> + TCGv addr = gen_get_xaddr(); >>> + >>> + tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ >>> + gen_data_store(ctx, Rd, addr); >>> + gen_set_xaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads one byte indirect with or without displacement from the data >>> space >>> + * to a register. For parts with SRAM, the data space consists of the >>> Register >>> + * File, I/O memory and internal SRAM (and external SRAM if >>> applicable). For >>> + * parts without SRAM, the data space consists of the Register File >>> only. In >>> + * some parts the Flash Memory has been mapped to the data space and >>> can be >>> + * read using this command. The EEPROM has a separate address space. >>> The data >>> + * location is pointed to by the Y (16 bits) Pointer Register in the >>> Register >>> + * File. Memory access is limited to the current data segment of 64KB. >>> To >>> + * access another data segment in devices with more than 64KB data >>> space, the >>> + * RAMPY in register in the I/O area has to be changed. The Y-pointer >>> Register >>> + * can either be left unchanged by the operation, or it can be >>> post-incremented >>> + * or predecremented. These features are especially suited for >>> accessing >>> + * arrays, tables, and Stack Pointer usage of the Y-pointer Register. >>> Note that >>> + * only the low byte of the Y-pointer is updated in devices with no >>> more than >>> + * 256 bytes data space. For such devices, the high byte of the >>> pointer is not >>> + * used by this instruction and can be used for other purposes. The >>> RAMPY >>> + * Register in the I/O area is updated in parts with more than 64KB >>> data space >>> + * or more than 64KB Program memory, and the >>> increment/decrement/displacement >>> + * is added to the entire 24-bit address on such devices. Not all >>> variants of >>> + * this instruction is available in all devices. Refer to the device >>> specific >>> + * instruction set summary. In the Reduced Core tinyAVR the LD >>> instruction can >>> + * be used to achieve the same operation as LPM since the program >>> memory is >>> + * mapped to the data memory space. >>> + */ >>> +static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_yaddr(); >>> + >>> + gen_data_load(ctx, Rd, addr); >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + >>> + gen_set_yaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_yaddr(); >>> + >>> + tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ >>> + gen_data_load(ctx, Rd, addr); >>> + gen_set_yaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_yaddr(); >>> + >>> + tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ >>> + gen_data_load(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STY2(DisasContext *ctx, arg_STY2 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_yaddr(); >>> + >>> + gen_data_store(ctx, Rd, addr); >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + gen_set_yaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STY3(DisasContext *ctx, arg_STY3 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_yaddr(); >>> + >>> + tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ >>> + gen_data_store(ctx, Rd, addr); >>> + gen_set_yaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STDY(DisasContext *ctx, arg_STDY *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_yaddr(); >>> + >>> + tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ >>> + gen_data_store(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads one byte indirect with or without displacement from the data >>> space >>> + * to a register. For parts with SRAM, the data space consists of the >>> Register >>> + * File, I/O memory and internal SRAM (and external SRAM if >>> applicable). For >>> + * parts without SRAM, the data space consists of the Register File >>> only. In >>> + * some parts the Flash Memory has been mapped to the data space and >>> can be >>> + * read using this command. The EEPROM has a separate address space. >>> The data >>> + * location is pointed to by the Z (16 bits) Pointer Register in the >>> Register >>> + * File. Memory access is limited to the current data segment of 64KB. >>> To >>> + * access another data segment in devices with more than 64KB data >>> space, the >>> + * RAMPZ in register in the I/O area has to be changed. The Z-pointer >>> Register >>> + * can either be left unchanged by the operation, or it can be >>> post-incremented >>> + * or predecremented. These features are especially suited for Stack >>> Pointer >>> + * usage of the Z-pointer Register, however because the Z-pointer >>> Register can >>> + * be used for indirect subroutine calls, indirect jumps and table >>> lookup, it >>> + * is often more convenient to use the X or Y-pointer as a dedicated >>> Stack >>> + * Pointer. Note that only the low byte of the Z-pointer is updated in >>> devices >>> + * with no more than 256 bytes data space. For such devices, the high >>> byte of >>> + * the pointer is not used by this instruction and can be used for >>> other >>> + * purposes. The RAMPZ Register in the I/O area is updated in parts >>> with more >>> + * than 64KB data space or more than 64KB Program memory, and the >>> + * increment/decrement/displacement is added to the entire 24-bit >>> address on >>> + * such devices. Not all variants of this instruction is available in >>> all >>> + * devices. Refer to the device specific instruction set summary. In >>> the >>> + * Reduced Core tinyAVR the LD instruction can be used to achieve the >>> same >>> + * operation as LPM since the program memory is mapped to the data >>> memory >>> + * space. For using the Z-pointer for table lookup in Program memory >>> see the >>> + * LPM and ELPM instructions. >>> + */ >>> +static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + gen_data_load(ctx, Rd, addr); >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + >>> + gen_set_zaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ >>> + gen_data_load(ctx, Rd, addr); >>> + >>> + gen_set_zaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ >>> + gen_data_load(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + gen_data_store(ctx, Rd, addr); >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + >>> + gen_set_zaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ >>> + gen_data_store(ctx, Rd, addr); >>> + >>> + gen_set_zaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ >>> + gen_data_store(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> + >>> +/* >>> + * Stores one byte from a Register to the data space. For parts with >>> SRAM, >>> + * the data space consists of the Register File, I/O memory and >>> internal SRAM >>> + * (and external SRAM if applicable). For parts without SRAM, the data >>> space >>> + * consists of the Register File only. The EEPROM has a separate >>> address space. >>> + * A 16-bit address must be supplied. Memory access is limited to the >>> current >>> + * data segment of 64KB. The STS instruction uses the RAMPD Register >>> to access >>> + * memory above 64KB. To access another data segment in devices with >>> more than >>> + * 64KB data space, the RAMPD in register in the I/O area has to be >>> changed. >>> + * This instruction is not available in all devices. Refer to the >>> device >>> + * specific instruction set summary. >>> + */ >>> +static bool trans_STS(DisasContext *ctx, arg_STS *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = tcg_temp_new_i32(); >>> + TCGv H = cpu_rampD; >>> + a->imm = next_word(ctx); >>> + >>> + tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ >>> + tcg_gen_shli_tl(addr, addr, 16); >>> + tcg_gen_ori_tl(addr, addr, a->imm); >>> + >>> + gen_data_store(ctx, Rd, addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads one byte pointed to by the Z-register into the destination >>> + * register Rd. This instruction features a 100% space effective >>> constant >>> + * initialization or constant data fetch. The Program memory is >>> organized in >>> + * 16-bit words while the Z-pointer is a byte address. Thus, the least >>> + * significant bit of the Z-pointer selects either low byte (ZLSB = 0) >>> or high >>> + * byte (ZLSB = 1). This instruction can address the first 64KB (32K >>> words) of >>> + * Program memory. The Zpointer Register can either be left unchanged >>> by the >>> + * operation, or it can be incremented. The incrementation does not >>> apply to >>> + * the RAMPZ Register. Devices with Self-Programming capability can >>> use the >>> + * LPM instruction to read the Fuse and Lock bit values. Refer to the >>> device >>> + * documentation for a detailed description. The LPM instruction is >>> not >>> + * available in all devices. Refer to the device specific instruction >>> set >>> + * summary >>> + */ >>> +static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[0]; >>> + TCGv addr = tcg_temp_new_i32(); >>> + TCGv H = cpu_r[31]; >>> + TCGv L = cpu_r[30]; >>> + >>> + tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ >>> + tcg_gen_or_tl(addr, addr, L); >>> + >>> + tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = tcg_temp_new_i32(); >>> + TCGv H = cpu_r[31]; >>> + TCGv L = cpu_r[30]; >>> + >>> + tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ >>> + tcg_gen_or_tl(addr, addr, L); >>> + >>> + tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = tcg_temp_new_i32(); >>> + TCGv H = cpu_r[31]; >>> + TCGv L = cpu_r[30]; >>> + >>> + tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ >>> + tcg_gen_or_tl(addr, addr, L); >>> + >>> + tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ >>> + >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + >>> + tcg_gen_andi_tl(L, addr, 0xff); >>> + >>> + tcg_gen_shri_tl(addr, addr, 8); >>> + tcg_gen_andi_tl(H, addr, 0xff); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads one byte pointed to by the Z-register and the RAMPZ Register >>> in >>> + * the I/O space, and places this byte in the destination register Rd. >>> This >>> + * instruction features a 100% space effective constant initialization >>> or >>> + * constant data fetch. The Program memory is organized in 16-bit >>> words while >>> + * the Z-pointer is a byte address. Thus, the least significant bit of >>> the >>> + * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = >>> 1). This >>> + * instruction can address the entire Program memory space. The >>> Z-pointer >>> + * Register can either be left unchanged by the operation, or it can be >>> + * incremented. The incrementation applies to the entire 24-bit >>> concatenation >>> + * of the RAMPZ and Z-pointer Registers. Devices with Self-Programming >>> + * capability can use the ELPM instruction to read the Fuse and Lock >>> bit value. >>> + * Refer to the device documentation for a detailed description. This >>> + * instruction is not available in all devices. Refer to the device >>> specific >>> + * instruction set summary. >>> + */ >>> +static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[0]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ >>> + >>> + tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ >>> + >>> + gen_set_zaddr(addr); >>> + >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * SPM can be used to erase a page in the Program memory, to write a >>> page >>> + * in the Program memory (that is already erased), and to set Boot >>> Loader Lock >>> + * bits. In some devices, the Program memory can be written one word >>> at a time, >>> + * in other devices an entire page can be programmed simultaneously >>> after first >>> + * filling a temporary page buffer. In all cases, the Program memory >>> must be >>> + * erased one page at a time. When erasing the Program memory, the >>> RAMPZ and >>> + * Z-register are used as page address. When writing the Program >>> memory, the >>> + * RAMPZ and Z-register are used as page or word address, and the R1:R0 >>> + * register pair is used as data(1). When setting the Boot Loader Lock >>> bits, >>> + * the R1:R0 register pair is used as data. Refer to the device >>> documentation >>> + * for detailed description of SPM usage. This instruction can address >>> the >>> + * entire Program memory. The SPM instruction is not available in all >>> devices. >>> + * Refer to the device specific instruction set summary. Note: 1. R1 >>> + * determines the instruction high byte, and R0 determines the >>> instruction low >>> + * byte. >>> + */ >>> +static bool trans_SPM(DisasContext *ctx, arg_SPM *a) >>> +{ >>> + /* TODO */ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) { >>> + return true; >>> + } >>> + >>> + return true; >>> +} >>> + >>> + >>> +static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) >>> +{ >>> + /* TODO */ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) { >>> + return true; >>> + } >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Loads data from the I/O Space (Ports, Timers, Configuration >>> Registers, >>> + * etc.) into register Rd in the Register File. >>> + */ >>> +static bool trans_IN(DisasContext *ctx, arg_IN *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv port = tcg_const_i32(a->imm); >>> + >>> + gen_helper_inb(Rd, cpu_env, port); >>> + >>> + tcg_temp_free_i32(port); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Stores data from register Rr in the Register File to I/O Space >>> (Ports, >>> + * Timers, Configuration Registers, etc.). >>> + */ >>> +static bool trans_OUT(DisasContext *ctx, arg_OUT *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv port = tcg_const_i32(a->imm); >>> + >>> + gen_helper_outb(cpu_env, port, Rd); >>> + >>> + tcg_temp_free_i32(port); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * This instruction stores the contents of register Rr on the STACK. >>> The >>> + * Stack Pointer is post-decremented by 1 after the PUSH. This >>> instruction is >>> + * not available in all devices. Refer to the device specific >>> instruction set >>> + * summary. >>> + */ >>> +static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + >>> + gen_data_store(ctx, Rd, cpu_sp); >>> + tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * This instruction loads register Rd with a byte from the STACK. The >>> Stack >>> + * Pointer is pre-incremented by 1 before the POP. This instruction >>> is not >>> + * available in all devices. Refer to the device specific instruction >>> set >>> + * summary. >>> + */ >>> +static bool trans_POP(DisasContext *ctx, arg_POP *a) >>> +{ >>> + /* >>> + * Using a temp to work around some strange behaviour: >>> + * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); >>> + * gen_data_load(ctx, Rd, cpu_sp); >>> + * seems to cause the add to happen twice. >>> + * This doesn't happen if either the add or the load is removed. >>> + */ >>> + TCGv t1 = tcg_temp_new_i32(); >>> + TCGv Rd = cpu_r[a->rd]; >>> + >>> + tcg_gen_addi_tl(t1, cpu_sp, 1); >>> + gen_data_load(ctx, Rd, t1); >>> + tcg_gen_mov_tl(cpu_sp, t1); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Exchanges one byte indirect between register and data space. The >>> data >>> + * location is pointed to by the Z (16 bits) Pointer Register in the >>> Register >>> + * File. Memory access is limited to the current data segment of 64KB. >>> To >>> + * access another data segment in devices with more than 64KB data >>> space, the >>> + * RAMPZ in register in the I/O area has to be changed. The Z-pointer >>> Register >>> + * is left unchanged by the operation. This instruction is especially >>> suited >>> + * for writing/reading status bits stored in SRAM. >>> + */ >>> +static bool trans_XCH(DisasContext *ctx, arg_XCH *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv t0 = tcg_temp_new_i32(); >>> + TCGv addr = gen_get_zaddr(); >>> + >>> + gen_data_load(ctx, t0, addr); >>> + gen_data_store(ctx, Rd, addr); >>> + tcg_gen_mov_tl(Rd, t0); >>> + >>> + tcg_temp_free_i32(t0); >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Load one byte indirect from data space to register and set bits in >>> data >>> + * space specified by the register. The instruction can only be used >>> towards >>> + * internal SRAM. The data location is pointed to by the Z (16 bits) >>> Pointer >>> + * Register in the Register File. Memory access is limited to the >>> current data >>> + * segment of 64KB. To access another data segment in devices with >>> more than >>> + * 64KB data space, the RAMPZ in register in the I/O area has to be >>> changed. >>> + * The Z-pointer Register is left unchanged by the operation. This >>> instruction >>> + * is especially suited for setting status bits stored in SRAM. >>> + */ >>> +static bool trans_LAS(DisasContext *ctx, arg_LAS *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { >>> + return true; >>> + } >>> + >>> + TCGv Rr = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + TCGv t0 = tcg_temp_new_i32(); >>> + TCGv t1 = tcg_temp_new_i32(); >>> + >>> + gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ >>> + tcg_gen_or_tl(t1, t0, Rr); >>> + >>> + tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ >>> + gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ >>> + >>> + tcg_temp_free_i32(t1); >>> + tcg_temp_free_i32(t0); >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Load one byte indirect from data space to register and stores and >>> clear >>> + * the bits in data space specified by the register. The instruction >>> can >>> + * only be used towards internal SRAM. The data location is pointed >>> to by >>> + * the Z (16 bits) Pointer Register in the Register File. Memory >>> access is >>> + * limited to the current data segment of 64KB. To access another data >>> + * segment in devices with more than 64KB data space, the RAMPZ in >>> register >>> + * in the I/O area has to be changed. The Z-pointer Register is left >>> + * unchanged by the operation. This instruction is especially suited >>> for >>> + * clearing status bits stored in SRAM. >>> + */ >>> +static bool trans_LAC(DisasContext *ctx, arg_LAC *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { >>> + return true; >>> + } >>> + >>> + TCGv Rr = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + TCGv t0 = tcg_temp_new_i32(); >>> + TCGv t1 = tcg_temp_new_i32(); >>> + >>> + gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ >>> + /* t1 = t0 & (0xff - Rr) = t0 and ~Rr */ >>> + tcg_gen_andc_tl(t1, t0, Rr); >>> + >>> + tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ >>> + gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ >>> + >>> + tcg_temp_free_i32(t1); >>> + tcg_temp_free_i32(t0); >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Load one byte indirect from data space to register and toggles bits >>> in >>> + * the data space specified by the register. The instruction can only >>> be used >>> + * towards SRAM. The data location is pointed to by the Z (16 bits) >>> Pointer >>> + * Register in the Register File. Memory access is limited to the >>> current data >>> + * segment of 64KB. To access another data segment in devices with >>> more than >>> + * 64KB data space, the RAMPZ in register in the I/O area has to be >>> changed. >>> + * The Z-pointer Register is left unchanged by the operation. This >>> instruction >>> + * is especially suited for changing status bits stored in SRAM. >>> + */ >>> +static bool trans_LAT(DisasContext *ctx, arg_LAT *a) >>> +{ >>> + if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { >>> + return true; >>> + } >>> + >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv addr = gen_get_zaddr(); >>> + TCGv t0 = tcg_temp_new_i32(); >>> + TCGv t1 = tcg_temp_new_i32(); >>> + >>> + gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ >>> + tcg_gen_xor_tl(t1, t0, Rd); >>> + >>> + tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */ >>> + gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ >>> + >>> + tcg_temp_free_i32(t1); >>> + tcg_temp_free_i32(t0); >>> + tcg_temp_free_i32(addr); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit >>> 0 is >>> + * loaded into the C Flag of the SREG. This operation effectively >>> divides an >>> + * unsigned value by two. The C Flag can be used to round the result. >>> + */ >>> +static bool trans_LSR(DisasContext *ctx, arg_LSR *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + >>> + tcg_gen_andi_tl(cpu_Cf, Rd, 1); >>> + >>> + tcg_gen_shri_tl(Rd, Rd, 1); >>> + >>> + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf = Rd == 0 */ >>> + tcg_gen_movi_tl(cpu_Nf, 0); >>> + tcg_gen_mov_tl(cpu_Vf, cpu_Cf); >>> + tcg_gen_mov_tl(cpu_Sf, cpu_Vf); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Shifts all bits in Rd one place to the right. The C Flag is shifted >>> into >>> + * bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, >>> combined >>> + * with ASR, effectively divides multi-byte signed values by two. >>> Combined with >>> + * LSR it effectively divides multi-byte unsigned values by two. The >>> Carry Flag >>> + * can be used to round the result. >>> + */ >>> +static bool trans_ROR(DisasContext *ctx, arg_ROR *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv t0 = tcg_temp_new_i32(); >>> + >>> + tcg_gen_shli_tl(t0, cpu_Cf, 7); >>> + tcg_gen_andi_tl(cpu_Cf, Rd, 1); >>> + tcg_gen_shri_tl(Rd, Rd, 1); >>> + tcg_gen_or_tl(Rd, Rd, t0); >>> + >>> + gen_rshift_ZNVSf(Rd); >>> + >>> + tcg_temp_free_i32(t0); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Shifts all bits in Rd one place to the right. Bit 7 is held >>> constant. Bit 0 >>> + * is loaded into the C Flag of the SREG. This operation effectively >>> divides a >>> + * signed value by two without changing its sign. The Carry Flag can >>> be used to >>> + * round the result. >>> + */ >>> +static bool trans_ASR(DisasContext *ctx, arg_ASR *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv t0 = tcg_temp_new_i32(); >>> + >>> + /* Cf */ >>> + tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */ >>> + >>> + /* op */ >>> + tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */ >>> + tcg_gen_shri_tl(Rd, Rd, 1); >>> + tcg_gen_or_tl(Rd, Rd, t0); >>> + >>> + gen_rshift_ZNVSf(Rd); >>> + >>> + tcg_temp_free_i32(t0); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Swaps high and low nibbles in a register. >>> + */ >>> +static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv t0 = tcg_temp_new_i32(); >>> + TCGv t1 = tcg_temp_new_i32(); >>> + >>> + tcg_gen_andi_tl(t0, Rd, 0x0f); >>> + tcg_gen_shli_tl(t0, t0, 4); >>> + tcg_gen_andi_tl(t1, Rd, 0xf0); >>> + tcg_gen_shri_tl(t1, t1, 4); >>> + tcg_gen_or_tl(Rd, t0, t1); >>> + >>> + tcg_temp_free_i32(t1); >>> + tcg_temp_free_i32(t0); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Sets a specified bit in an I/O Register. This instruction operates >>> on >>> + * the lower 32 I/O Registers -- addresses 0-31. >>> + */ >>> +static bool trans_SBI(DisasContext *ctx, arg_SBI *a) >>> +{ >>> + TCGv data = tcg_temp_new_i32(); >>> + TCGv port = tcg_const_i32(a->reg); >>> + >>> + gen_helper_inb(data, cpu_env, port); >>> + tcg_gen_ori_tl(data, data, 1 << a->bit); >>> + gen_helper_outb(cpu_env, port, data); >>> + >>> + tcg_temp_free_i32(port); >>> + tcg_temp_free_i32(data); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Clears a specified bit in an I/O Register. This instruction >>> operates on >>> + * the lower 32 I/O Registers -- addresses 0-31. >>> + */ >>> +static bool trans_CBI(DisasContext *ctx, arg_CBI *a) >>> +{ >>> + TCGv data = tcg_temp_new_i32(); >>> + TCGv port = tcg_const_i32(a->reg); >>> + >>> + gen_helper_inb(data, cpu_env, port); >>> + tcg_gen_andi_tl(data, data, ~(1 << a->bit)); >>> + gen_helper_outb(cpu_env, port, data); >>> + >>> + tcg_temp_free_i32(data); >>> + tcg_temp_free_i32(port); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Stores bit b from Rd to the T Flag in SREG (Status Register). >>> + */ >>> +static bool trans_BST(DisasContext *ctx, arg_BST *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + >>> + tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit); >>> + tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Copies the T Flag in the SREG (Status Register) to bit b in >>> register Rd. >>> + */ >>> +static bool trans_BLD(DisasContext *ctx, arg_BLD *a) >>> +{ >>> + TCGv Rd = cpu_r[a->rd]; >>> + TCGv t1 = tcg_temp_new_i32(); >>> + >>> + tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ >>> + tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ >>> + tcg_gen_or_tl(Rd, Rd, t1); >>> + >>> + tcg_temp_free_i32(t1); >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Sets a single Flag or bit in SREG. >>> + */ >>> +static bool trans_BSET(DisasContext *ctx, arg_BSET *a) >>> +{ >>> + switch (a->bit) { >>> + case 0x00: >>> + tcg_gen_movi_tl(cpu_Cf, 0x01); >>> + break; >>> + case 0x01: >>> + tcg_gen_movi_tl(cpu_Zf, 0x01); >>> + break; >>> + case 0x02: >>> + tcg_gen_movi_tl(cpu_Nf, 0x01); >>> + break; >>> + case 0x03: >>> + tcg_gen_movi_tl(cpu_Vf, 0x01); >>> + break; >>> + case 0x04: >>> + tcg_gen_movi_tl(cpu_Sf, 0x01); >>> + break; >>> + case 0x05: >>> + tcg_gen_movi_tl(cpu_Hf, 0x01); >>> + break; >>> + case 0x06: >>> + tcg_gen_movi_tl(cpu_Tf, 0x01); >>> + break; >>> + case 0x07: >>> + tcg_gen_movi_tl(cpu_If, 0x01); >>> + break; >>> + } >>> + >>> + return true; >>> +} >>> + >>> + >>> +/* >>> + * Clears a single Flag in SREG. >>> + */ >>> +static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a) >>> +{ >>> + switch (a->bit) { >>> + case 0x00: >>> + tcg_gen_movi_tl(cpu_Cf, 0x00); >>> + break; >>> + case 0x01: >>> + tcg_gen_movi_tl(cpu_Zf, 0x00); >>> + break; >>> + case 0x02: >>> + tcg_gen_movi_tl(cpu_Nf, 0x00); >>> + break; >>> + case 0x03: >>> + tcg_gen_movi_tl(cpu_Vf, 0x00); >>> + break; >>> + case 0x04: >>> + tcg_gen_movi_tl(cpu_Sf, 0x00); >>> + break; >>> + case 0x05: >>> + tcg_gen_movi_tl(cpu_Hf, 0x00); >>> + break; >>> + case 0x06: >>> + tcg_gen_movi_tl(cpu_Tf, 0x00); >>> + break; >>> + case 0x07: >>> + tcg_gen_movi_tl(cpu_If, 0x00); >>> + break; >>> + } >>> + >>> + return true; >>> +} >>> -- >>> 2.17.2 (Apple Git-113) >>> >>> > > -- > Best Regards, > Michael Rolnik > -- Best Regards, Michael Rolnik --0000000000005fc2ac0598f4eb78 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
my mistake. Thanks. I will split it.

On Thu, Dec 5, 2019 = at 3:17 PM Michael Rolnik <mrolnik@= gmail.com> wrote:
I think they do follow the division in the docs= .

On Thu, Dec 5, 2019 at 2:28 PM Aleksandar Markovic <aleksandar.m.mail@gmail.com> wrote:

On Wednesday, November 27, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex">This includes:
=C2=A0 =C2=A0 - LSR, ROR
=C2=A0 =C2=A0 - ASR
=C2=A0 =C2=A0 - SWAP
=C2=A0 =C2=A0 - SBI, CBI
=C2=A0 =C2=A0 - BST, BLD
=C2=A0 =C2=A0 - BSET, BCLR

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
=C2=A0target/avr/translate.c | 1123 +++++++++++++++++++++++++++++++++++++++= +
=C2=A01 file changed, 1123 insertions(+)


Hello, Michael

I said I am on vacation, and truly I am, but, fir the next version if the= series, I would like to ask you to extract "data transfer" instr= uction (as defined in avr docs, MOV LD ST etc) from this patch, and create = a new patch for them - so that the patches follow the division from docs.

Yours,
Aleksandar



=C2=A0
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 48a42c984a..dc6a1af2fc 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -317,6 +317,15 @@ static void gen_goto_tb(DisasContext *ctx, int n, targ= et_ulong dest)
=C2=A0}


+static void gen_rshift_ZNVSf(TCGv R)
+{
+=C2=A0 =C2=A0 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf =3D R = =3D=3D 0 */
+=C2=A0 =C2=A0 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf =3D R(7) */
+=C2=A0 =C2=A0 tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);
+=C2=A0 =C2=A0 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf =3D Nf ^ Vf */=
+}
+
+
=C2=A0/*
=C2=A0 *=C2=A0 Adds two registers without the C Flag and places the result = in the
=C2=A0 *=C2=A0 destination register Rd.
@@ -1508,3 +1517,1117 @@ static bool trans_BRBS(DisasContext *ctx, arg_BRBS= *a)
=C2=A0 =C2=A0 =C2=A0return true;
=C2=A0}

+
+/*
+ *=C2=A0 This instruction makes a copy of one register into another. The s= ource
+ *=C2=A0 register Rr is left unchanged, while the destination register Rd = is loaded
+ *=C2=A0 with a copy of Rr.
+ */
+static bool trans_MOV(DisasContext *ctx, arg_MOV *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv Rr =3D cpu_r[a->rr];
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(Rd, Rr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 This instruction makes a copy of one register pair into another r= egister
+ *=C2=A0 pair. The source register pair Rr+1:Rr is left unchanged, while t= he
+ *=C2=A0 destination register pair Rd+1:Rd is loaded with a copy of Rr + 1= :Rr.=C2=A0 This
+ *=C2=A0 instruction is not available in all devices. Refer to the device = specific
+ *=C2=A0 instruction set summary.
+ */
+static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv RdL =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv RdH =3D cpu_r[a->rd + 1];
+=C2=A0 =C2=A0 TCGv RrL =3D cpu_r[a->rr];
+=C2=A0 =C2=A0 TCGv RrH =3D cpu_r[a->rr + 1];
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(RdH, RrH);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(RdL, RrL);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ * Loads an 8 bit constant directly to register 16 to 31.
+ */
+static bool trans_LDI(DisasContext *ctx, arg_LDI *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 int imm =3D a->imm;
+
+=C2=A0 =C2=A0 tcg_gen_movi_tl(Rd, imm);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads one byte from the data space to a register. For parts with = SRAM,
+ *=C2=A0 the data space consists of the Register File, I/O memory and inte= rnal SRAM
+ *=C2=A0 (and external SRAM if applicable). For parts without SRAM, the da= ta space
+ *=C2=A0 consists of the register file only. The EEPROM has a separate add= ress space.
+ *=C2=A0 A 16-bit address must be supplied. Memory access is limited to th= e current
+ *=C2=A0 data segment of 64KB. The LDS instruction uses the RAMPD Register= to access
+ *=C2=A0 memory above 64KB. To access another data segment in devices with= more than
+ *=C2=A0 64KB data space, the RAMPD in register in the I/O area has to be = changed.
+ *=C2=A0 This instruction is not available in all devices. Refer to the de= vice
+ *=C2=A0 specific instruction set summary.
+ */
+static bool trans_LDS(DisasContext *ctx, arg_LDS *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv H =3D cpu_rampD;
+=C2=A0 =C2=A0 a->imm =3D next_word(ctx);
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */
+=C2=A0 =C2=A0 tcg_gen_shli_tl(addr, addr, 16);
+=C2=A0 =C2=A0 tcg_gen_ori_tl(addr, addr, a->imm);
+
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads one byte indirect from the data space to a register. For pa= rts
+ *=C2=A0 with SRAM, the data space consists of the Register File, I/O memo= ry and
+ *=C2=A0 internal SRAM (and external SRAM if applicable). For parts withou= t SRAM, the
+ *=C2=A0 data space consists of the Register File only. In some parts the = Flash
+ *=C2=A0 Memory has been mapped to the data space and can be read using th= is command.
+ *=C2=A0 The EEPROM has a separate address space.=C2=A0 The data location = is pointed to by
+ *=C2=A0 the X (16 bits) Pointer Register in the Register File. Memory acc= ess is
+ *=C2=A0 limited to the current data segment of 64KB. To access another da= ta segment
+ *=C2=A0 in devices with more than 64KB data space, the RAMPX in register = in the I/O
+ *=C2=A0 area has to be changed.=C2=A0 The X-pointer Register can either b= e left unchanged
+ *=C2=A0 by the operation, or it can be post-incremented or predecremented= .=C2=A0 These
+ *=C2=A0 features are especially suited for accessing arrays, tables, and = Stack
+ *=C2=A0 Pointer usage of the X-pointer Register. Note that only the low b= yte of the
+ *=C2=A0 X-pointer is updated in devices with no more than 256 bytes data = space. For
+ *=C2=A0 such devices, the high byte of the pointer is not used by this in= struction
+ *=C2=A0 and can be used for other purposes. The RAMPX Register in the I/O= area is
+ *=C2=A0 updated in parts with more than 64KB data space or more than 64KB= Program
+ *=C2=A0 memory, and the increment/decrement is added to the entire 24-bit= address on
+ *=C2=A0 such devices.=C2=A0 Not all variants of this instruction is avail= able in all
+ *=C2=A0 devices. Refer to the device specific instruction set summary.=C2= =A0 In the
+ *=C2=A0 Reduced Core tinyAVR the LD instruction can be used to achieve th= e same
+ *=C2=A0 operation as LPM since the program memory is mapped to the data m= emory
+ *=C2=A0 space.
+ */
+static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_xaddr();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_xaddr();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+
+=C2=A0 =C2=A0 gen_set_xaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_xaddr();
+
+=C2=A0 =C2=A0 tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+=C2=A0 =C2=A0 gen_set_xaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STX1(DisasContext *ctx, arg_STX1 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rr];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_xaddr();
+
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+static bool trans_STX2(DisasContext *ctx, arg_STX2 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rr];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_xaddr();
+
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+=C2=A0 =C2=A0 gen_set_xaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+static bool trans_STX3(DisasContext *ctx, arg_STX3 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rr];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_xaddr();
+
+=C2=A0 =C2=A0 tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+=C2=A0 =C2=A0 gen_set_xaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads one byte indirect with or without displacement from the dat= a space
+ *=C2=A0 to a register. For parts with SRAM, the data space consists of th= e Register
+ *=C2=A0 File, I/O memory and internal SRAM (and external SRAM if applicab= le). For
+ *=C2=A0 parts without SRAM, the data space consists of the Register File = only. In
+ *=C2=A0 some parts the Flash Memory has been mapped to the data space and= can be
+ *=C2=A0 read using this command. The EEPROM has a separate address space.= =C2=A0 The data
+ *=C2=A0 location is pointed to by the Y (16 bits) Pointer Register in the= Register
+ *=C2=A0 File. Memory access is limited to the current data segment of 64K= B. To
+ *=C2=A0 access another data segment in devices with more than 64KB data s= pace, the
+ *=C2=A0 RAMPY in register in the I/O area has to be changed.=C2=A0 The Y-= pointer Register
+ *=C2=A0 can either be left unchanged by the operation, or it can be post-= incremented
+ *=C2=A0 or predecremented.=C2=A0 These features are especially suited for= accessing
+ *=C2=A0 arrays, tables, and Stack Pointer usage of the Y-pointer Register= . Note that
+ *=C2=A0 only the low byte of the Y-pointer is updated in devices with no = more than
+ *=C2=A0 256 bytes data space. For such devices, the high byte of the poin= ter is not
+ *=C2=A0 used by this instruction and can be used for other purposes. The = RAMPY
+ *=C2=A0 Register in the I/O area is updated in parts with more than 64KB = data space
+ *=C2=A0 or more than 64KB Program memory, and the increment/decrement/dis= placement
+ *=C2=A0 is added to the entire 24-bit address on such devices.=C2=A0 Not = all variants of
+ *=C2=A0 this instruction is available in all devices. Refer to the device= specific
+ *=C2=A0 instruction set summary.=C2=A0 In the Reduced Core tinyAVR the LD= instruction can
+ *=C2=A0 be used to achieve the same operation as LPM since the program me= mory is
+ *=C2=A0 mapped to the data memory space.
+ */
+static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_yaddr();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+
+=C2=A0 =C2=A0 gen_set_yaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_yaddr();
+
+=C2=A0 =C2=A0 tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+=C2=A0 =C2=A0 gen_set_yaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_yaddr();
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q= */
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STY2(DisasContext *ctx, arg_STY2 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_yaddr();
+
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+=C2=A0 =C2=A0 gen_set_yaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STY3(DisasContext *ctx, arg_STY3 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_yaddr();
+
+=C2=A0 =C2=A0 tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+=C2=A0 =C2=A0 gen_set_yaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STDY(DisasContext *ctx, arg_STDY *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_yaddr();
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q= */
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads one byte indirect with or without displacement from the dat= a space
+ *=C2=A0 to a register. For parts with SRAM, the data space consists of th= e Register
+ *=C2=A0 File, I/O memory and internal SRAM (and external SRAM if applicab= le). For
+ *=C2=A0 parts without SRAM, the data space consists of the Register File = only. In
+ *=C2=A0 some parts the Flash Memory has been mapped to the data space and= can be
+ *=C2=A0 read using this command. The EEPROM has a separate address space.= =C2=A0 The data
+ *=C2=A0 location is pointed to by the Z (16 bits) Pointer Register in the= Register
+ *=C2=A0 File. Memory access is limited to the current data segment of 64K= B. To
+ *=C2=A0 access another data segment in devices with more than 64KB data s= pace, the
+ *=C2=A0 RAMPZ in register in the I/O area has to be changed.=C2=A0 The Z-= pointer Register
+ *=C2=A0 can either be left unchanged by the operation, or it can be post-= incremented
+ *=C2=A0 or predecremented.=C2=A0 These features are especially suited for= Stack Pointer
+ *=C2=A0 usage of the Z-pointer Register, however because the Z-pointer Re= gister can
+ *=C2=A0 be used for indirect subroutine calls, indirect jumps and table l= ookup, it
+ *=C2=A0 is often more convenient to use the X or Y-pointer as a dedicated= Stack
+ *=C2=A0 Pointer. Note that only the low byte of the Z-pointer is updated = in devices
+ *=C2=A0 with no more than 256 bytes data space. For such devices, the hig= h byte of
+ *=C2=A0 the pointer is not used by this instruction and can be used for o= ther
+ *=C2=A0 purposes. The RAMPZ Register in the I/O area is updated in parts = with more
+ *=C2=A0 than 64KB data space or more than 64KB Program memory, and the + *=C2=A0 increment/decrement/displacement is added to the entire 24-bit ad= dress on
+ *=C2=A0 such devices.=C2=A0 Not all variants of this instruction is avail= able in all
+ *=C2=A0 devices. Refer to the device specific instruction set summary.=C2= =A0 In the
+ *=C2=A0 Reduced Core tinyAVR the LD instruction can be used to achieve th= e same
+ *=C2=A0 operation as LPM since the program memory is mapped to the data m= emory
+ *=C2=A0 space.=C2=A0 For using the Z-pointer for table lookup in Program = memory see the
+ *=C2=A0 LPM and ELPM instructions.
+ */
+static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+
+=C2=A0 =C2=A0 gen_set_zaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 gen_set_zaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q= */
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+
+=C2=A0 =C2=A0 gen_set_zaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 gen_set_zaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q= */
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+
+/*
+ *=C2=A0 Stores one byte from a Register to the data space. For parts with= SRAM,
+ *=C2=A0 the data space consists of the Register File, I/O memory and inte= rnal SRAM
+ *=C2=A0 (and external SRAM if applicable). For parts without SRAM, the da= ta space
+ *=C2=A0 consists of the Register File only. The EEPROM has a separate add= ress space.
+ *=C2=A0 A 16-bit address must be supplied. Memory access is limited to th= e current
+ *=C2=A0 data segment of 64KB. The STS instruction uses the RAMPD Register= to access
+ *=C2=A0 memory above 64KB. To access another data segment in devices with= more than
+ *=C2=A0 64KB data space, the RAMPD in register in the I/O area has to be = changed.
+ *=C2=A0 This instruction is not available in all devices. Refer to the de= vice
+ *=C2=A0 specific instruction set summary.
+ */
+static bool trans_STS(DisasContext *ctx, arg_STS *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv H =3D cpu_rampD;
+=C2=A0 =C2=A0 a->imm =3D next_word(ctx);
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */
+=C2=A0 =C2=A0 tcg_gen_shli_tl(addr, addr, 16);
+=C2=A0 =C2=A0 tcg_gen_ori_tl(addr, addr, a->imm);
+
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads one byte pointed to by the Z-register into the destination<= br> + *=C2=A0 register Rd. This instruction features a 100% space effective con= stant
+ *=C2=A0 initialization or constant data fetch. The Program memory is orga= nized in
+ *=C2=A0 16-bit words while the Z-pointer is a byte address. Thus, the lea= st
+ *=C2=A0 significant bit of the Z-pointer selects either low byte (ZLSB = =3D 0) or high
+ *=C2=A0 byte (ZLSB =3D 1). This instruction can address the first 64KB (3= 2K words) of
+ *=C2=A0 Program memory. The Zpointer Register can either be left unchange= d by the
+ *=C2=A0 operation, or it can be incremented. The incrementation does not = apply to
+ *=C2=A0 the RAMPZ Register.=C2=A0 Devices with Self-Programming capabilit= y can use the
+ *=C2=A0 LPM instruction to read the Fuse and Lock bit values.=C2=A0 Refer= to the device
+ *=C2=A0 documentation for a detailed description.=C2=A0 The LPM instructi= on is not
+ *=C2=A0 available in all devices. Refer to the device specific instructio= n set
+ *=C2=A0 summary
+ */
+static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[0];
+=C2=A0 =C2=A0 TCGv addr =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv H =3D cpu_r[31];
+=C2=A0 =C2=A0 TCGv L =3D cpu_r[30];
+
+=C2=A0 =C2=A0 tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */
+=C2=A0 =C2=A0 tcg_gen_or_tl(addr, addr, L);
+
+=C2=A0 =C2=A0 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[add= r] */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv H =3D cpu_r[31];
+=C2=A0 =C2=A0 TCGv L =3D cpu_r[30];
+
+=C2=A0 =C2=A0 tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */
+=C2=A0 =C2=A0 tcg_gen_or_tl(addr, addr, L);
+
+=C2=A0 =C2=A0 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[add= r] */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv H =3D cpu_r[31];
+=C2=A0 =C2=A0 TCGv L =3D cpu_r[30];
+
+=C2=A0 =C2=A0 tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */
+=C2=A0 =C2=A0 tcg_gen_or_tl(addr, addr, L);
+
+=C2=A0 =C2=A0 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[add= r] */
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+
+=C2=A0 =C2=A0 tcg_gen_andi_tl(L, addr, 0xff);
+
+=C2=A0 =C2=A0 tcg_gen_shri_tl(addr, addr, 8);
+=C2=A0 =C2=A0 tcg_gen_andi_tl(H, addr, 0xff);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads one byte pointed to by the Z-register and the RAMPZ Registe= r in
+ *=C2=A0 the I/O space, and places this byte in the destination register R= d. This
+ *=C2=A0 instruction features a 100% space effective constant initializati= on or
+ *=C2=A0 constant data fetch. The Program memory is organized in 16-bit wo= rds while
+ *=C2=A0 the Z-pointer is a byte address. Thus, the least significant bit = of the
+ *=C2=A0 Z-pointer selects either low byte (ZLSB =3D 0) or high byte (ZLSB= =3D 1). This
+ *=C2=A0 instruction can address the entire Program memory space. The Z-po= inter
+ *=C2=A0 Register can either be left unchanged by the operation, or it can= be
+ *=C2=A0 incremented. The incrementation applies to the entire 24-bit conc= atenation
+ *=C2=A0 of the RAMPZ and Z-pointer Registers.=C2=A0 Devices with Self-Pro= gramming
+ *=C2=A0 capability can use the ELPM instruction to read the Fuse and Lock= bit value.
+ *=C2=A0 Refer to the device documentation for a detailed description.=C2= =A0 This
+ *=C2=A0 instruction is not available in all devices. Refer to the device = specific
+ *=C2=A0 instruction set summary.
+ */
+static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[0];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[add= r] */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[add= r] */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[add= r] */
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */
+
+=C2=A0 =C2=A0 gen_set_zaddr(addr);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 SPM can be used to erase a page in the Program memory, to write a= page
+ *=C2=A0 in the Program memory (that is already erased), and to set Boot L= oader Lock
+ *=C2=A0 bits. In some devices, the Program memory can be written one word= at a time,
+ *=C2=A0 in other devices an entire page can be programmed simultaneously = after first
+ *=C2=A0 filling a temporary page buffer. In all cases, the Program memory= must be
+ *=C2=A0 erased one page at a time. When erasing the Program memory, the R= AMPZ and
+ *=C2=A0 Z-register are used as page address. When writing the Program mem= ory, the
+ *=C2=A0 RAMPZ and Z-register are used as page or word address, and the R1= :R0
+ *=C2=A0 register pair is used as data(1). When setting the Boot Loader Lo= ck bits,
+ *=C2=A0 the R1:R0 register pair is used as data. Refer to the device docu= mentation
+ *=C2=A0 for detailed description of SPM usage. This instruction can addre= ss the
+ *=C2=A0 entire Program memory.=C2=A0 The SPM instruction is not available= in all devices.
+ *=C2=A0 Refer to the device specific instruction set summary.=C2=A0 Note:= 1. R1
+ *=C2=A0 determines the instruction high byte, and R0 determines the instr= uction low
+ *=C2=A0 byte.
+ */
+static bool trans_SPM(DisasContext *ctx, arg_SPM *a)
+{
+=C2=A0 =C2=A0 /* TODO */
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
+{
+=C2=A0 =C2=A0 /* TODO */
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Loads data from the I/O Space (Ports, Timers, Configuration Regis= ters,
+ *=C2=A0 etc.) into register Rd in the Register File.
+ */
+static bool trans_IN(DisasContext *ctx, arg_IN *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv port =3D tcg_const_i32(a->imm);
+
+=C2=A0 =C2=A0 gen_helper_inb(Rd, cpu_env, port);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(port);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Stores data from register Rr in the Register File to I/O Space (P= orts,
+ *=C2=A0 Timers, Configuration Registers, etc.).
+ */
+static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv port =3D tcg_const_i32(a->imm);
+
+=C2=A0 =C2=A0 gen_helper_outb(cpu_env, port, Rd);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(port);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 This instruction stores the contents of register Rr on the STACK.= The
+ *=C2=A0 Stack Pointer is post-decremented by 1 after the PUSH.=C2=A0 This= instruction is
+ *=C2=A0 not available in all devices. Refer to the device specific instru= ction set
+ *=C2=A0 summary.
+ */
+static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, cpu_sp);
+=C2=A0 =C2=A0 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 This instruction loads register Rd with a byte from the STACK. Th= e Stack
+ *=C2=A0 Pointer is pre-incremented by 1 before the POP.=C2=A0 This instru= ction is not
+ *=C2=A0 available in all devices. Refer to the device specific instructio= n set
+ *=C2=A0 summary.
+ */
+static bool trans_POP(DisasContext *ctx, arg_POP *a)
+{
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* Using a temp to work around some strange behaviour:<= br> +=C2=A0 =C2=A0 =C2=A0* tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+=C2=A0 =C2=A0 =C2=A0* gen_data_load(ctx, Rd, cpu_sp);
+=C2=A0 =C2=A0 =C2=A0* seems to cause the add to happen twice.
+=C2=A0 =C2=A0 =C2=A0* This doesn't happen if either the add or the loa= d is removed.
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 TCGv t1 =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+
+=C2=A0 =C2=A0 tcg_gen_addi_tl(t1, cpu_sp, 1);
+=C2=A0 =C2=A0 gen_data_load(ctx, Rd, t1);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(cpu_sp, t1);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Exchanges one byte indirect between register and data space.=C2= =A0 The data
+ *=C2=A0 location is pointed to by the Z (16 bits) Pointer Register in the= Register
+ *=C2=A0 File. Memory access is limited to the current data segment of 64K= B. To
+ *=C2=A0 access another data segment in devices with more than 64KB data s= pace, the
+ *=C2=A0 RAMPZ in register in the I/O area has to be changed.=C2=A0 The Z-= pointer Register
+ *=C2=A0 is left unchanged by the operation. This instruction is especiall= y suited
+ *=C2=A0 for writing/reading status bits stored in SRAM.
+ */
+static bool trans_XCH(DisasContext *ctx, arg_XCH *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, t0, addr);
+=C2=A0 =C2=A0 gen_data_store(ctx, Rd, addr);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(Rd, t0);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Load one byte indirect from data space to register and set bits i= n data
+ *=C2=A0 space specified by the register. The instruction can only be used= towards
+ *=C2=A0 internal SRAM.=C2=A0 The data location is pointed to by the Z (16= bits) Pointer
+ *=C2=A0 Register in the Register File. Memory access is limited to the cu= rrent data
+ *=C2=A0 segment of 64KB. To access another data segment in devices with m= ore than
+ *=C2=A0 64KB data space, the RAMPZ in register in the I/O area has to be = changed.
+ *=C2=A0 The Z-pointer Register is left unchanged by the operation. This i= nstruction
+ *=C2=A0 is especially suited for setting status bits stored in SRAM.
+ */
+static bool trans_LAS(DisasContext *ctx, arg_LAS *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rr =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv t1 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, t0, addr); /* t0 =3D mem[addr] */
+=C2=A0 =C2=A0 tcg_gen_or_tl(t1, t0, Rr);
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(Rr, t0); /* Rr =3D t0 */
+=C2=A0 =C2=A0 gen_data_store(ctx, t1, addr); /* mem[addr] =3D t1 */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t1);
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Load one byte indirect from data space to register and stores and= clear
+ *=C2=A0 the bits in data space specified by the register. The instruction= can
+ *=C2=A0 only be used towards internal SRAM.=C2=A0 The data location is po= inted to by
+ *=C2=A0 the Z (16 bits) Pointer Register in the Register File. Memory acc= ess is
+ *=C2=A0 limited to the current data segment of 64KB. To access another da= ta
+ *=C2=A0 segment in devices with more than 64KB data space, the RAMPZ in r= egister
+ *=C2=A0 in the I/O area has to be changed.=C2=A0 The Z-pointer Register i= s left
+ *=C2=A0 unchanged by the operation. This instruction is especially suited= for
+ *=C2=A0 clearing status bits stored in SRAM.
+ */
+static bool trans_LAC(DisasContext *ctx, arg_LAC *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rr =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv t1 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, t0, addr); /* t0 =3D mem[addr] */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* t1 =3D t0 & (0xff - Rr) =3D t0 and ~Rr = */
+=C2=A0 =C2=A0 tcg_gen_andc_tl(t1, t0, Rr);
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(Rr, t0); /* Rr =3D t0 */
+=C2=A0 =C2=A0 gen_data_store(ctx, t1, addr); /* mem[addr] =3D t1 */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t1);
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Load one byte indirect from data space to register and toggles bi= ts in
+ *=C2=A0 the data space specified by the register.=C2=A0 The instruction c= an only be used
+ *=C2=A0 towards SRAM.=C2=A0 The data location is pointed to by the Z (16 = bits) Pointer
+ *=C2=A0 Register in the Register File. Memory access is limited to the cu= rrent data
+ *=C2=A0 segment of 64KB. To access another data segment in devices with m= ore than
+ *=C2=A0 64KB data space, the RAMPZ in register in the I/O area has to be = changed.
+ *=C2=A0 The Z-pointer Register is left unchanged by the operation. This i= nstruction
+ *=C2=A0 is especially suited for changing status bits stored in SRAM.
+ */
+static bool trans_LAT(DisasContext *ctx, arg_LAT *a)
+{
+=C2=A0 =C2=A0 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv addr =3D gen_get_zaddr();
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv t1 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 gen_data_load(ctx, t0, addr); /* t0 =3D mem[addr] */
+=C2=A0 =C2=A0 tcg_gen_xor_tl(t1, t0, Rd);
+
+=C2=A0 =C2=A0 tcg_gen_mov_tl(Rd, t0); /* Rd =3D t0 */
+=C2=A0 =C2=A0 gen_data_store(ctx, t1, addr); /* mem[addr] =3D t1 */
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t1);
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+=C2=A0 =C2=A0 tcg_temp_free_i32(addr);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Shifts all bits in Rd one place to the right. Bit 7 is cleared. B= it 0 is
+ *=C2=A0 loaded into the C Flag of the SREG. This operation effectively di= vides an
+ *=C2=A0 unsigned value by two. The C Flag can be used to round the result= .
+ */
+static bool trans_LSR(DisasContext *ctx, arg_LSR *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+
+=C2=A0 =C2=A0 tcg_gen_andi_tl(cpu_Cf, Rd, 1);
+
+=C2=A0 =C2=A0 tcg_gen_shri_tl(Rd, Rd, 1);
+
+=C2=A0 =C2=A0 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf =3D R= d =3D=3D 0 */
+=C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Nf, 0);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(cpu_Vf, cpu_Cf);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(cpu_Sf, cpu_Vf);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Shifts all bits in Rd one place to the right. The C Flag is shift= ed into
+ *=C2=A0 bit 7 of Rd. Bit 0 is shifted into the C Flag.=C2=A0 This operati= on, combined
+ *=C2=A0 with ASR, effectively divides multi-byte signed values by two. Co= mbined with
+ *=C2=A0 LSR it effectively divides multi-byte unsigned values by two. The= Carry Flag
+ *=C2=A0 can be used to round the result.
+ */
+static bool trans_ROR(DisasContext *ctx, arg_ROR *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 tcg_gen_shli_tl(t0, cpu_Cf, 7);
+=C2=A0 =C2=A0 tcg_gen_andi_tl(cpu_Cf, Rd, 1);
+=C2=A0 =C2=A0 tcg_gen_shri_tl(Rd, Rd, 1);
+=C2=A0 =C2=A0 tcg_gen_or_tl(Rd, Rd, t0);
+
+=C2=A0 =C2=A0 gen_rshift_ZNVSf(Rd);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Shifts all bits in Rd one place to the right. Bit 7 is held const= ant. Bit 0
+ *=C2=A0 is loaded into the C Flag of the SREG. This operation effectively= divides a
+ *=C2=A0 signed value by two without changing its sign. The Carry Flag can= be used to
+ *=C2=A0 round the result.
+ */
+static bool trans_ASR(DisasContext *ctx, arg_ASR *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 /* Cf */
+=C2=A0 =C2=A0 tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf =3D Rd(0) */
+
+=C2=A0 =C2=A0 /* op */
+=C2=A0 =C2=A0 tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd =3D (Rd & 0x80) | (= Rd >> 1) */
+=C2=A0 =C2=A0 tcg_gen_shri_tl(Rd, Rd, 1);
+=C2=A0 =C2=A0 tcg_gen_or_tl(Rd, Rd, t0);
+
+=C2=A0 =C2=A0 gen_rshift_ZNVSf(Rd);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Swaps high and low nibbles in a register.
+ */
+static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv t0 =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv t1 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 tcg_gen_andi_tl(t0, Rd, 0x0f);
+=C2=A0 =C2=A0 tcg_gen_shli_tl(t0, t0, 4);
+=C2=A0 =C2=A0 tcg_gen_andi_tl(t1, Rd, 0xf0);
+=C2=A0 =C2=A0 tcg_gen_shri_tl(t1, t1, 4);
+=C2=A0 =C2=A0 tcg_gen_or_tl(Rd, t0, t1);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t1);
+=C2=A0 =C2=A0 tcg_temp_free_i32(t0);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Sets a specified bit in an I/O Register. This instruction operate= s on
+ *=C2=A0 the lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
+{
+=C2=A0 =C2=A0 TCGv data =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv port =3D tcg_const_i32(a->reg);
+
+=C2=A0 =C2=A0 gen_helper_inb(data, cpu_env, port);
+=C2=A0 =C2=A0 tcg_gen_ori_tl(data, data, 1 << a->bit);
+=C2=A0 =C2=A0 gen_helper_outb(cpu_env, port, data);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(port);
+=C2=A0 =C2=A0 tcg_temp_free_i32(data);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Clears a specified bit in an I/O Register. This instruction opera= tes on
+ *=C2=A0 the lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
+{
+=C2=A0 =C2=A0 TCGv data =3D tcg_temp_new_i32();
+=C2=A0 =C2=A0 TCGv port =3D tcg_const_i32(a->reg);
+
+=C2=A0 =C2=A0 gen_helper_inb(data, cpu_env, port);
+=C2=A0 =C2=A0 tcg_gen_andi_tl(data, data, ~(1 << a->bit));
+=C2=A0 =C2=A0 gen_helper_outb(cpu_env, port, data);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(data);
+=C2=A0 =C2=A0 tcg_temp_free_i32(port);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Stores bit b from Rd to the T Flag in SREG (Status Register).
+ */
+static bool trans_BST(DisasContext *ctx, arg_BST *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+
+=C2=A0 =C2=A0 tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit);
+=C2=A0 =C2=A0 tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Copies the T Flag in the SREG (Status Register) to bit b in regis= ter Rd.
+ */
+static bool trans_BLD(DisasContext *ctx, arg_BLD *a)
+{
+=C2=A0 =C2=A0 TCGv Rd =3D cpu_r[a->rd];
+=C2=A0 =C2=A0 TCGv t1 =3D tcg_temp_new_i32();
+
+=C2=A0 =C2=A0 tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear = bit */
+=C2=A0 =C2=A0 tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ +=C2=A0 =C2=A0 tcg_gen_or_tl(Rd, Rd, t1);
+
+=C2=A0 =C2=A0 tcg_temp_free_i32(t1);
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Sets a single Flag or bit in SREG.
+ */
+static bool trans_BSET(DisasContext *ctx, arg_BSET *a)
+{
+=C2=A0 =C2=A0 switch (a->bit) {
+=C2=A0 =C2=A0 case 0x00:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Cf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x01:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Zf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x02:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Nf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x03:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Vf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x04:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Sf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x05:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Hf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x06:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Tf, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x07:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_If, 0x01);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 return true;
+}
+
+
+/*
+ *=C2=A0 Clears a single Flag in SREG.
+ */
+static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
+{
+=C2=A0 =C2=A0 switch (a->bit) {
+=C2=A0 =C2=A0 case 0x00:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Cf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x01:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Zf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x02:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Nf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x03:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Vf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x04:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Sf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x05:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Hf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x06:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_Tf, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 0x07:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_movi_tl(cpu_If, 0x00);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 return true;
+}
--
2.17.2 (Apple Git-113)



--
Best Regards,
Michael Rolnik


--
Best Regards,
Michael Rolnik
--0000000000005fc2ac0598f4eb78--