From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65199C433B4 for ; Mon, 3 May 2021 20:10:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F535611AB for ; Mon, 3 May 2021 20:10:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F535611AB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:35712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldeu0-0003rG-7U for qemu-devel@archiver.kernel.org; Mon, 03 May 2021 16:10:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldesI-0002lm-Pn for qemu-devel@nongnu.org; Mon, 03 May 2021 16:09:02 -0400 Received: from mail-qk1-x72d.google.com ([2607:f8b0:4864:20::72d]:35405) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ldesE-0003N3-DU for qemu-devel@nongnu.org; Mon, 03 May 2021 16:09:02 -0400 Received: by mail-qk1-x72d.google.com with SMTP id x8so6416580qkl.2 for ; Mon, 03 May 2021 13:08:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=u1x5b5uwU6AcJ0OUMMzK8rBxg/PV6ZIUD9m0yUkP+Oc=; b=P7YmeTOCQrF10jOP7yrNPMjdu/O7ZSJP4yGo34QvMOsqaRuH1tTQP4QNAZonWAlN5K CmSN+uohB0GeczJcAQNBtRg4b3CIlBdbwq5YNhbYPX1Rinot2IACXKTat9ZCANg/jGzq xStcQdoDK8wA0zqT3U9qp93uKu/sA2I3TcrZ2HmFSUM5Lc30VIdtP4NDFtTrol2T9yl2 J7SwcYE9pYOP10pGqraVuoKwOsUQs4gQvp/G0/D1SvpujNQumsV8O/831yfyCT3M4bLj sffKJhWZxQXcbeWudAS+Ci8aTv8AIfNVZFpF05dniBZWXhdqisA16IXYkMzrdG8gTvcG CiHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=u1x5b5uwU6AcJ0OUMMzK8rBxg/PV6ZIUD9m0yUkP+Oc=; b=ZKuldXWPRXy/7LDhN082qlkuvsHj/Stqltb8cLJN2fjJxrvNh5kZ57QQ7HwTdz554G 6a+ADbn0+WF1L1cLNkyqssf7ReWVYRmgAE3TTykBXlyhfTV9P9TD8/x7njA4yzfAibvI KKP2MpOt3rE02vTcoigCBkfvZVAw7Jp8C7bFYGDnCzZwYynxJC3DB8p09hhyBnSelDuV sVJfIYYv6mWcWhbmlgTcwDjuM13gGghL5AuacShpGcgKpO/aIVDs6ytxGDbrAjWL4mOM 6elTjUFiHm3D5DFKuEG7Gd3sONdO0QbvFanxxGeVP4eTQDSCAnguKrx6+eyW7Py/Z3e4 yEZA== X-Gm-Message-State: AOAM531g/ZvSo/We799uvVeWWltqmq+4KdSLXjaCE4AC/uNooLz7V5Wu dgsaJcx+8B5NPPceTBcK5cfHtMJ/q3SeA3FJb+Q= X-Google-Smtp-Source: ABdhPJyIZm8lhkxOR1QTqRgD6tTJ+HeVyEOvm/tKjyeQAzrr5p0V7Py5ej9J4X9zkUTT3I3VQxuSxrm+Xh58iMNGTnM= X-Received: by 2002:ae9:f302:: with SMTP id p2mr20418011qkg.103.1620072536362; Mon, 03 May 2021 13:08:56 -0700 (PDT) MIME-Version: 1.0 References: <20210502201040.52296-1-mrolnik@gmail.com> <20210502201040.52296-3-mrolnik@gmail.com> In-Reply-To: From: Michael Rolnik Date: Mon, 3 May 2021 23:08:19 +0300 Message-ID: Subject: Re: [RFC 1/1] Implement AVR watchdog timer To: Fred Konrad Content-Type: multipart/alternative; boundary="0000000000000a510f05c17288e0" Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=mrolnik@gmail.com; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joaquin de Andres , Richard Henderson , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000000a510f05c17288e0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi all, I was about to make icount work. but, there is something I still don't understand. I have this code timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_wdt_interrupt, s); and then void avr_wdt_interrupt(/* some arguments */) { #define MS2NS(n) ((n) * 1000000ull) timer_mod_ns(timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + MS2NS(15)); } when running with --icount shift=3D0, *avr_wdt_interrupt* is called about every 1K instructions, however it should have been called 15M instructions as shift=3D0 makes every instruction to be executed in 1 virtual ns. What am I doing wrong? Thank you, Michael Rolnik On Mon, May 3, 2021 at 4:36 PM Michael Rolnik wrote: > Hi Fred. > > 1. thanks > 2. It seems I have forgotten to set those flags. > 3. 15ms is easy to test 8s will take 533 times longer, so in my case 3200 > instructions which is totally incorrect. I don't understand why as > I program the timer in virtual nanoseconds and not host time. > 4. I hope Richard could help with icount. > > best regards, > Michael Rolnik > > On Mon, May 3, 2021 at 4:15 PM Fred Konrad wrote: > >> >> >> Le 5/2/21 =C3=A0 10:10 PM, Michael Rolnik a =C3=A9crit : >> > Signed-off-by: Michael Rolnik >> > --- >> > hw/avr/Kconfig | 1 + >> > hw/avr/atmega.c | 15 ++- >> > hw/avr/atmega.h | 2 + >> > hw/watchdog/Kconfig | 3 + >> > hw/watchdog/avr_wdt.c | 190 ++++++++++++++++++++++++++++++++= ++ >> > hw/watchdog/meson.build | 2 + >> > hw/watchdog/trace-events | 5 + >> > include/hw/watchdog/avr_wdt.h | 47 +++++++++ >> > target/avr/cpu.c | 3 + >> > target/avr/cpu.h | 1 + >> > target/avr/helper.c | 7 +- >> > 11 files changed, 271 insertions(+), 5 deletions(-) >> > create mode 100644 hw/watchdog/avr_wdt.c >> > create mode 100644 include/hw/watchdog/avr_wdt.h >> > >> > diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig >> > index d31298c3cc..9939e4902f 100644 >> > --- a/hw/avr/Kconfig >> > +++ b/hw/avr/Kconfig >> > @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU >> > select AVR_TIMER16 >> > select AVR_USART >> > select AVR_POWER >> > + select AVR_WDT >> > >> > config ARDUINO >> > select AVR_ATMEGA_MCU >> > diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c >> > index 44c6afebbb..31ceb1c21c 100644 >> > --- a/hw/avr/atmega.c >> > +++ b/hw/avr/atmega.c >> > @@ -28,6 +28,7 @@ enum AtmegaPeripheral { >> > GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL, >> > USART0, USART1, USART2, USART3, >> > TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5, >> > + WDT, >> > PERIFMAX >> > }; >> > >> > @@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] =3D= { >> > [GPIOD] =3D { 0x29 }, >> > [GPIOC] =3D { 0x26 }, >> > [GPIOB] =3D { 0x23 }, >> > + [WDT] =3D { 0x60 }, >> > }, dev1280_2560[PERIFMAX] =3D { >> > [USART3] =3D { 0x130, POWER1, 2 }, >> > [TIMER5] =3D { 0x120, POWER1, 5, 0x73, 0x3a, true }, >> > @@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = =3D { >> > [GPIOC] =3D { 0x26 }, >> > [GPIOB] =3D { 0x23 }, >> > [GPIOA] =3D { 0x20 }, >> > + [WDT] =3D { 0x60 }, >> > }; >> > >> > enum AtmegaIrq { >> > @@ -118,6 +121,7 @@ enum AtmegaIrq { >> > TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ, >> > TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ, >> > TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ, >> > + WATCHDOG_TIMER_IRQ, >> > IRQ_COUNT >> > }; >> > >> > @@ -133,6 +137,7 @@ enum AtmegaIrq { >> > #define TIMER_OVF_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ) >> > >> > static const uint8_t irq168_328[IRQ_COUNT] =3D { >> > + [WATCHDOG_TIMER_IRQ] =3D 7, >> > [TIMER2_COMPA_IRQ] =3D 8, >> > [TIMER2_COMPB_IRQ] =3D 9, >> > [TIMER2_OVF_IRQ] =3D 10, >> > @@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] =3D { >> > [USART0_DRE_IRQ] =3D 20, >> > [USART0_TXC_IRQ] =3D 21, >> > }, irq1280_2560[IRQ_COUNT] =3D { >> > + [WATCHDOG_TIMER_IRQ] =3D 13, >> > [TIMER2_COMPA_IRQ] =3D 14, >> > [TIMER2_COMPB_IRQ] =3D 15, >> > [TIMER2_OVF_IRQ] =3D 16, >> > @@ -344,10 +350,17 @@ static void atmega_realize(DeviceState *dev, >> Error **errp) >> > g_free(devname); >> > } >> > >> > + /* Watchdog Timer */ >> > + object_initialize_child(OBJECT(dev), "wdt", &s->wdt, TYPE_AVR_WDT= ); >> > + sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); >> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, >> > + OFFSET_DATA + mc->dev[WDT].addr); >> > + qdev_connect_gpio_out_named(cpudev, "wdr", 0, >> > + qdev_get_gpio_in_named(DEVICE(&s->wdt), "wdr", 0)= ); >> > + >> > create_unimplemented_device("avr-twi", OFFSET_DATA + >> 0x0b8, 6); >> > create_unimplemented_device("avr-adc", OFFSET_DATA + >> 0x078, 8); >> > create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + >> 0x074, 2); >> > - create_unimplemented_device("avr-watchdog", OFFSET_DATA + >> 0x060, 1); >> > create_unimplemented_device("avr-spi", OFFSET_DATA + >> 0x04c, 3); >> > create_unimplemented_device("avr-eeprom", OFFSET_DATA + >> 0x03f, 3); >> > } >> > diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h >> > index a99ee15c7e..60bbd44bdd 100644 >> > --- a/hw/avr/atmega.h >> > +++ b/hw/avr/atmega.h >> > @@ -13,6 +13,7 @@ >> > >> > #include "hw/char/avr_usart.h" >> > #include "hw/timer/avr_timer16.h" >> > +#include "hw/watchdog/avr_wdt.h" >> > #include "hw/misc/avr_power.h" >> > #include "target/avr/cpu.h" >> > #include "qom/object.h" >> > @@ -45,6 +46,7 @@ struct AtmegaMcuState { >> > AVRMaskState pwr[POWER_MAX]; >> > AVRUsartState usart[USART_MAX]; >> > AVRTimer16State timer[TIMER_MAX]; >> > + AVRWatchdogState wdt; >> > uint64_t xtal_freq_hz; >> > }; >> > >> > diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig >> > index 66e1d029e3..e0f89d2fe0 100644 >> > --- a/hw/watchdog/Kconfig >> > +++ b/hw/watchdog/Kconfig >> > @@ -20,3 +20,6 @@ config WDT_IMX2 >> > >> > config WDT_SBSA >> > bool >> > + >> > +config AVR_WDT >> > + bool >> > diff --git a/hw/watchdog/avr_wdt.c b/hw/watchdog/avr_wdt.c >> > new file mode 100644 >> > index 0000000000..4ce1029a64 >> > --- /dev/null >> > +++ b/hw/watchdog/avr_wdt.c >> > @@ -0,0 +1,190 @@ >> > +/* >> > + * AVR watchdog >> > + * >> > + * Copyright (c) 2018 Michael Rolnik >> >> 2021? >> >> > + * >> > + * This library is free software; you can redistribute it and/or >> > + * modify it under the terms of the GNU Lesser General Public >> > + * License as published by the Free Software Foundation; either >> > + * version 2.1 of the License, or (at your option) any later version. >> > + * >> > + * This library is distributed in the hope that it will be useful, >> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU >> > + * Lesser General Public License for more details. >> > + * >> > + * You should have received a copy of the GNU Lesser General Public >> > + * License along with this library; if not, see >> > + * >> > + */ >> > + >> > +#include "qemu/osdep.h" >> > +#include "qapi/error.h" >> > +#include "qemu/log.h" >> > +#include "hw/irq.h" >> > +#include "hw/watchdog/avr_wdt.h" >> > +#include "trace.h" >> > + >> > +/* Field masks */ >> > +#define WDTCSR_MASK_WDP0 0x01 >> > +#define WDTCSR_MASK_WDP1 0x02 >> > +#define WDTCSR_MASK_WDP2 0x04 >> > +#define WDTCSR_MASK_WDE 0x08 >> > +#define WDTCSR_MASK_WCE 0x10 >> > +#define WDTCSR_MASK_WDP3 0x20 >> > +#define WDTCSR_MASK_WDIE 0x40 >> > +#define WDTCSR_MASK_WDIF 0x80 >> > + >> > +#define WDTCSR_SHFT_WDP0 0x00 >> > +#define WDTCSR_SHFT_WDP1 0x01 >> > +#define WDTCSR_SHFT_WDP2 0x02 >> > +#define WDTCSR_SHFT_WDE 0x03 >> > +#define WDTCSR_SHFT_WCE 0x04 >> > +#define WDTCSR_SHFT_WDP3 0x05 >> > +#define WDTCSR_SHFT_WDIE 0x06 >> > +#define WDTCSR_SHFT_WDIF 0x07 >> > + >> > +/* Helper macros */ >> > +#define WDP0(csr) ((csr & WDTCSR_MASK_WDP0) >> WDTCSR_SHFT_WDP0= ) >> > +#define WDP1(csr) ((csr & WDTCSR_MASK_WDP1) >> WDTCSR_SHFT_WDP1= ) >> > +#define WDP2(csr) ((csr & WDTCSR_MASK_WDP2) >> WDTCSR_SHFT_WDP2= ) >> > +#define WDP3(csr) ((csr & WDTCSR_MASK_WDP3) >> WDTCSR_SHFT_WDP3= ) >> > +#define WDP(csr) ((WDP3(csr) << 3) | (WDP2(csr) << 2) | \ >> > + (WDP1(csr) << 1) | (WDP0(csr) << 0)) >> > +#define WDIE(csr) ((csr & WDTCSR_MASK_WDIE) >> WDTCSR_SHFT_WDIE= ) >> > +#define WDE(csr) ((csr & WDTCSR_MASK_WDE) >> WDTCSR_SHFT_WDE) >> > +#define WCE(csr) ((csr & WDTCSR_MASK_WCE) >> WDTCSR_SHFT_WCE) >> > + >> > +#define DB_PRINT(fmt, args...) /* Nothing */ >> > + >> > +#define MS2NS(n) ((n) * 1000000ull) >> > + >> > +static void avr_wdt_reset_alarm(AVRWatchdogState *wdt) >> > +{ >> > + uint32_t csr =3D wdt->csr; >> > + int wdp =3D WDP(csr); >> > + assert(wdp <=3D 9); >> >> Maybe qemu_log(..) instead and pick a default value? >> >> > + >> > + if (WDIE(csr) =3D=3D 0 && WDE(csr) =3D=3D 0) { >> > + /* watchdog is stopped */ >> > + return; >> > + } >> > + >> > + timer_mod_ns(wdt->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + >> > + (MS2NS(15) << wdp)); >> > +} >> > + >> > +static void avr_wdt_interrupt(void *opaque) >> > +{ >> > + AVRWatchdogState *wdt =3D opaque; >> > + int8_t csr =3D wdt->csr; >> > + >> > + if (WDE(csr) =3D=3D 0 && WDIE(csr) =3D=3D 0) { >> > + /* Stopped */ >> > + >> > + } else if (WDE(csr) =3D=3D 0 && WDIE(csr) =3D=3D 1) { >> > + /* Interrupt Mode */ >> > + wdt->csr |=3D WDTCSR_MASK_WDIF; >> > + qemu_set_irq(wdt->irq, 1); >> > + trace_avr_wdt_interrupt(); >> > + } else if (WDE(csr) =3D=3D 1 && WDIE(csr) =3D=3D 0) { >> > + /* System Reset Mode */ >> >> qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); >> >> +/- setting the MCUSR, WDRF flags would be nice. >> >> > + } else if (WDE(csr) =3D=3D 1 && WDIE(csr) =3D=3D 1) { >> > + /* Interrupt and System Reset Mode */ >> > + wdt->csr |=3D WDTCSR_MASK_WDIF; >> > + qemu_set_irq(wdt->irq, 1); >> > + trace_avr_wdt_interrupt(); >> > + } >> > + >> > + avr_wdt_reset_alarm(wdt); >> > +} >> > + >> > +static void avr_wdt_reset(DeviceState *dev) >> > +{ >> > + AVRWatchdogState *wdt =3D AVR_WDT(dev); >> > + >> > + wdt->csr =3D 0; >> > + qemu_set_irq(wdt->irq, 0); >> > + avr_wdt_reset_alarm(wdt); >> > +} >> > + >> > +static uint64_t avr_wdt_read(void *opaque, hwaddr offset, unsigned >> size) >> > +{ >> > + assert(size =3D=3D 1); >> > + AVRWatchdogState *wdt =3D opaque; >> > + uint8_t retval =3D wdt->csr; >> > + >> > + trace_avr_wdt_read(offset, retval); >> > + >> > + return (uint64_t)retval; >> > +} >> > + >> > +static void avr_wdt_write(void *opaque, hwaddr offset, >> > + uint64_t val64, unsigned size) >> > +{ >> > + assert(size =3D=3D 1); >> > + AVRWatchdogState *wdt =3D opaque; >> > + uint8_t val8 =3D (uint8_t)val64; >> > + >> > + trace_avr_wdt_write(offset, val8); >> > + >> > + wdt->csr =3D val8; >> > + avr_wdt_reset_alarm(wdt); >> > +} >> > + >> > +static const MemoryRegionOps avr_wdt_ops =3D { >> > + .read =3D avr_wdt_read, >> > + .write =3D avr_wdt_write, >> > + .endianness =3D DEVICE_NATIVE_ENDIAN, >> > + .impl =3D {.max_access_size =3D 1} >> > +}; >> > + >> > +static void avr_wdt_wdr(void *opaque, int irq, int level) >> > +{ >> > + AVRWatchdogState *wdt =3D AVR_WDT(opaque); >> > + >> > + avr_wdt_reset_alarm(wdt); >> > +} >> > + >> > +static void avr_wdt_init(Object *obj) >> > +{ >> > + AVRWatchdogState *s =3D AVR_WDT(obj); >> > + >> > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); >> > + >> > + memory_region_init_io(&s->iomem, obj, &avr_wdt_ops, >> > + s, "avr-wdt", 0xa); >> > + >> > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); >> > + qdev_init_gpio_in_named(DEVICE(s), avr_wdt_wdr, "wdr", 1); >> > +} >> > + >> > +static void avr_wdt_realize(DeviceState *dev, Error **errp) >> > +{ >> > + AVRWatchdogState *s =3D AVR_WDT(dev); >> > + >> > + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_wdt_interrupt, = s); >> > +} >> > + >> > +static void avr_wdt_class_init(ObjectClass *klass, void *data) >> > +{ >> > + DeviceClass *dc =3D DEVICE_CLASS(klass); >> > + >> > + dc->reset =3D avr_wdt_reset; >> > + dc->realize =3D avr_wdt_realize; >> > +} >> > + >> > +static const TypeInfo avr_wdt_info =3D { >> > + .name =3D TYPE_AVR_WDT, >> > + .parent =3D TYPE_SYS_BUS_DEVICE, >> > + .instance_size =3D sizeof(AVRWatchdogState), >> > + .instance_init =3D avr_wdt_init, >> > + .class_init =3D avr_wdt_class_init, >> > +}; >> > + >> > +static void avr_wdt_register_types(void) >> > +{ >> > + type_register_static(&avr_wdt_info); >> > +} >> > + >> > +type_init(avr_wdt_register_types) >> > diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build >> > index 054c403dea..8db2be8317 100644 >> > --- a/hw/watchdog/meson.build >> > +++ b/hw/watchdog/meson.build >> > @@ -6,3 +6,5 @@ softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: >> files('wdt_diag288.c')) >> > softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: >> files('wdt_aspeed.c')) >> > softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c')= ) >> > softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c'= )) >> > + >> > +specific_ss.add(when: 'CONFIG_AVR_WDT', if_true: files('avr_wdt.c')) >> > diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events >> > index 3124ca1f1b..ac14773179 100644 >> > --- a/hw/watchdog/trace-events >> > +++ b/hw/watchdog/trace-events >> > @@ -5,3 +5,8 @@ cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data= , >> unsigned size) "CMSDK AP >> > cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned >> size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " >> size %u" >> > cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset" >> > cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB watchdog: lock %" >> PRIu32 >> > + >> > +# avr_wdt.c >> > +avr_wdt_read(uint8_t addr, uint8_t value) "wdt read addr:%u value:%u" >> > +avr_wdt_write(uint8_t addr, uint8_t value) "wdt write addr:%u value:%= u" >> > +avr_wdt_interrupt(void) "" >> > diff --git a/include/hw/watchdog/avr_wdt.h >> b/include/hw/watchdog/avr_wdt.h >> > new file mode 100644 >> > index 0000000000..2679e8f2a6 >> > --- /dev/null >> > +++ b/include/hw/watchdog/avr_wdt.h >> > @@ -0,0 +1,47 @@ >> > +/* >> > + * AVR 16-bit timer >> >> AVR Watchdog? >> >> > + * >> > + * Copyright (c) 2021 Michael Rolnik >> > + * >> > + * This library is free software; you can redistribute it and/or >> > + * modify it under the terms of the GNU Lesser General Public >> > + * License as published by the Free Software Foundation; either >> > + * version 2.1 of the License, or (at your option) any later version. >> > + * >> > + * This library is distributed in the hope that it will be useful, >> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU >> > + * Lesser General Public License for more details. >> > + * >> > + * You should have received a copy of the GNU Lesser General Public >> > + * License along with this library; if not, see >> > + * >> > + */ >> > + >> > +#ifndef HW_WATCHDOG_AVR_WDT_H >> > +#define HW_WATCHDOG_AVR_WDT_H >> > + >> > +#include "hw/sysbus.h" >> > +#include "qemu/timer.h" >> > +#include "hw/hw.h" >> > +#include "qom/object.h" >> > + >> > +#define TYPE_AVR_WDT "avr-wdt" >> > +OBJECT_DECLARE_SIMPLE_TYPE(AVRWatchdogState, AVR_WDT) >> > + >> > +struct AVRWatchdogState { >> > + /* */ >> > + SysBusDevice parent_obj; >> > + >> > + /* */ >> > + MemoryRegion iomem; >> > + MemoryRegion imsk_iomem; >> > + MemoryRegion ifr_iomem; >> > + QEMUTimer *timer; >> > + qemu_irq irq; >> > + >> > + /* registers */ >> > + uint8_t csr; >> > +}; >> > + >> > +#endif /* HW_WATCHDOG_AVR_WDT_H */ >> > diff --git a/target/avr/cpu.c b/target/avr/cpu.c >> > index 0f4596932b..d5eb785833 100644 >> > --- a/target/avr/cpu.c >> > +++ b/target/avr/cpu.c >> > @@ -131,6 +131,9 @@ static void avr_cpu_initfn(Object *obj) >> > /* Set the number of interrupts supported by the CPU. */ >> > qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, >> > sizeof(cpu->env.intsrc) * 8); >> > + >> > + /* register watchdog timer reset interrupt */ >> > + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->wdr, "wdr", 1); >> > } >> > >> > static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) >> > diff --git a/target/avr/cpu.h b/target/avr/cpu.h >> > index d148e8c75a..f8f5641c8b 100644 >> > --- a/target/avr/cpu.h >> > +++ b/target/avr/cpu.h >> > @@ -152,6 +152,7 @@ typedef struct AVRCPU { >> > >> > CPUNegativeOffsetState neg; >> > CPUAVRState env; >> > + qemu_irq wdr; /* reset WDT */ >> > } AVRCPU; >> > >> > extern const struct VMStateDescription vms_avr_cpu; >> > diff --git a/target/avr/helper.c b/target/avr/helper.c >> > index 35e1019594..dd88057e5f 100644 >> > --- a/target/avr/helper.c >> > +++ b/target/avr/helper.c >> > @@ -24,6 +24,7 @@ >> > #include "exec/exec-all.h" >> > #include "exec/address-spaces.h" >> > #include "exec/helper-proto.h" >> > +#include "hw/irq.h" >> > >> > bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) >> > { >> > @@ -188,11 +189,9 @@ void helper_break(CPUAVRState *env) >> > >> > void helper_wdr(CPUAVRState *env) >> > { >> > - CPUState *cs =3D env_cpu(env); >> > + AVRCPU *cpu =3D env_archcpu(env); >> > >> > - /* WD is not implemented yet, placeholder */ >> > - cs->exception_index =3D EXCP_DEBUG; >> > - cpu_loop_exit(cs); >> > + qemu_set_irq(cpu->wdr, 1); >> > } >> > >> > /* >> > >> >> Thanks! >> > > > -- > Best Regards, > Michael Rolnik > --=20 Best Regards, Michael Rolnik --0000000000000a510f05c17288e0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi all,

I was about to make icoun= t work. but, there is something=C2=A0I still don't understand. I have t= his code=C2=A0

timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_wdt_interrup= t, s);

= and then

void=C2=A0avr_wd= t_interrupt(/* some arguments */) {
#define MS2NS(n) =C2=A0 =C2=A0 =C2=A0 =C2=A0((n) * 1000000ull)
=C2=A0 =C2=A0 timer_mod_n= s(timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +=C2=A0MS2NS(15));
}

when running with --ic= ount shift=3D0,=C2=A0avr_wdt_interrupt is called about every 1K instructions, however it should have bee= n called 15M instructions as shift=3D0 make= s every instruction to be executed in 1 virtual ns.

What am I doing wrong?

Thank you,
= Michael Rolnik


On Mon, May 3, 2021 at 4:36 PM Michael R= olnik <mrolnik@gmail.com> wr= ote:
Hi Fred.

1. thanks
2. It seem= s I have forgotten=C2=A0to set those flags.
3. 15ms is easy to te= st 8s will take 533 times longer, so in my case 3200 instructions which is = totally incorrect. I don't understand why as I=C2=A0program the timer i= n virtual nanoseconds and not host time.
4. I hope Richard could = help with icount.

best regards,
Michael = Rolnik

On Mon, May 3, 2021 at 4:15 PM Fred Konrad <konrad@adacore.com> wrote:


Le 5/2/21 =C3=A0 10:10 PM, Michael Rolnik a =C3=A9crit=C2=A0:
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> ---
>=C2=A0 =C2=A0hw/avr/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0hw/avr/atmega.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 15 ++-
>=C2=A0 =C2=A0hw/avr/atmega.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A02 +
>=C2=A0 =C2=A0hw/watchdog/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0|=C2=A0 =C2=A03 +
>=C2=A0 =C2=A0hw/watchdog/avr_wdt.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 1= 90 ++++++++++++++++++++++++++++++++++
>=C2=A0 =C2=A0hw/watchdog/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 = =C2=A02 +
>=C2=A0 =C2=A0hw/watchdog/trace-events=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A05 +
>=C2=A0 =C2=A0include/hw/watchdog/avr_wdt.h |=C2=A0 47 +++++++++
>=C2=A0 =C2=A0target/avr/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 =C2=A03 +
>=C2=A0 =C2=A0target/avr/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0target/avr/helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0|=C2=A0 =C2=A07 +-
>=C2=A0 =C2=A011 files changed, 271 insertions(+), 5 deletions(-)
>=C2=A0 =C2=A0create mode 100644 hw/watchdog/avr_wdt.c
>=C2=A0 =C2=A0create mode 100644 include/hw/watchdog/avr_wdt.h
>
> diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
> index d31298c3cc..9939e4902f 100644
> --- a/hw/avr/Kconfig
> +++ b/hw/avr/Kconfig
> @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select AVR_TIMER16
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select AVR_USART
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select AVR_POWER
> +=C2=A0 =C2=A0 select AVR_WDT
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0config ARDUINO
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select AVR_ATMEGA_MCU
> diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> index 44c6afebbb..31ceb1c21c 100644
> --- a/hw/avr/atmega.c
> +++ b/hw/avr/atmega.c
> @@ -28,6 +28,7 @@ enum AtmegaPeripheral {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL, >=C2=A0 =C2=A0 =C2=A0 =C2=A0USART0, USART1, USART2, USART3,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIME= R5,
> +=C2=A0 =C2=A0 WDT,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0PERIFMAX
>=C2=A0 =C2=A0};
>=C2=A0 =C2=A0
> @@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] =3D= {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[GPIOD]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= {=C2=A0 0x29 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[GPIOC]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= {=C2=A0 0x26 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[GPIOB]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= {=C2=A0 0x23 },
> +=C2=A0 =C2=A0 [WDT]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D {=C2= =A0 0x60 },
>=C2=A0 =C2=A0}, dev1280_2560[PERIFMAX] =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[USART3]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D { 0x= 130, POWER1, 2 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER5]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D { 0x= 120, POWER1, 5, 0x73, 0x3a, true },
> @@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[GPIOC]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= {=C2=A0 0x26 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[GPIOB]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= {=C2=A0 0x23 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[GPIOA]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D= {=C2=A0 0x20 },
> +=C2=A0 =C2=A0 [WDT]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D {=C2= =A0 0x60 },
>=C2=A0 =C2=A0};
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0enum AtmegaIrq {
> @@ -118,6 +121,7 @@ enum AtmegaIrq {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TIMER4_COMPC_IRQ, TIMER4_OVF_I= RQ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_CO= MPB_IRQ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TIMER5_COMPC_IRQ, TIMER5_OVF_I= RQ,
> +=C2=A0 =C2=A0 WATCHDOG_TIMER_IRQ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0IRQ_COUNT
>=C2=A0 =C2=A0};
>=C2=A0 =C2=A0
> @@ -133,6 +137,7 @@ enum AtmegaIrq {
>=C2=A0 =C2=A0#define TIMER_OVF_IRQ(n)=C2=A0 =C2=A0 (n * TIMER_IRQ_COUNT= + TIMER0_OVF_IRQ)
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0static const uint8_t irq168_328[IRQ_COUNT] =3D {
> +=C2=A0 =C2=A0 [WATCHDOG_TIMER_IRQ]=C2=A0 =C2=A0 =3D 7,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER2_COMPA_IRQ]=C2=A0 =C2=A0 =C2=A0 =3D 8= ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER2_COMPB_IRQ]=C2=A0 =C2=A0 =C2=A0 =3D 9= ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER2_OVF_IRQ]=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =3D 10,
> @@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] =3D { >=C2=A0 =C2=A0 =C2=A0 =C2=A0[USART0_DRE_IRQ]=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =3D 20,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[USART0_TXC_IRQ]=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =3D 21,
>=C2=A0 =C2=A0}, irq1280_2560[IRQ_COUNT] =3D {
> +=C2=A0 =C2=A0 [WATCHDOG_TIMER_IRQ]=C2=A0 =C2=A0 =3D 13,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER2_COMPA_IRQ]=C2=A0 =C2=A0 =C2=A0 =3D 1= 4,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER2_COMPB_IRQ]=C2=A0 =C2=A0 =C2=A0 =3D 1= 5,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[TIMER2_OVF_IRQ]=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =3D 16,
> @@ -344,10 +350,17 @@ static void atmega_realize(DeviceState *dev, Err= or **errp)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0g_free(devname);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Watchdog Timer */
> +=C2=A0 =C2=A0 object_initialize_child(OBJECT(dev), "wdt", &= amp;s->wdt, TYPE_AVR_WDT);
> +=C2=A0 =C2=A0 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &err= or_abort);
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= OFFSET_DATA + mc->dev[WDT].addr);
> +=C2=A0 =C2=A0 qdev_connect_gpio_out_named(cpudev, "wdr", 0,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= qdev_get_gpio_in_named(DEVICE(&s->wdt), "wdr", 0));
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0create_unimplemented_device("avr-twi&qu= ot;,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OFFSET_DATA + 0x0b8, 6);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0create_unimplemented_device("avr-adc&qu= ot;,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OFFSET_DATA + 0x078, 8);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0create_unimplemented_device("avr-ext-me= m-ctrl", OFFSET_DATA + 0x074, 2);
> -=C2=A0 =C2=A0 create_unimplemented_device("avr-watchdog",= =C2=A0 =C2=A0 =C2=A0OFFSET_DATA + 0x060, 1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0create_unimplemented_device("avr-spi&qu= ot;,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OFFSET_DATA + 0x04c, 3);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0create_unimplemented_device("avr-eeprom= ",=C2=A0 =C2=A0 =C2=A0 =C2=A0OFFSET_DATA + 0x03f, 3);
>=C2=A0 =C2=A0}
> diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
> index a99ee15c7e..60bbd44bdd 100644
> --- a/hw/avr/atmega.h
> +++ b/hw/avr/atmega.h
> @@ -13,6 +13,7 @@
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0#include "hw/char/avr_usart.h"
>=C2=A0 =C2=A0#include "hw/timer/avr_timer16.h"
> +#include "hw/watchdog/avr_wdt.h"
>=C2=A0 =C2=A0#include "hw/misc/avr_power.h"
>=C2=A0 =C2=A0#include "target/avr/cpu.h"
>=C2=A0 =C2=A0#include "qom/object.h"
> @@ -45,6 +46,7 @@ struct AtmegaMcuState {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AVRMaskState pwr[POWER_MAX];
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AVRUsartState usart[USART_MAX];
>=C2=A0 =C2=A0 =C2=A0 =C2=A0AVRTimer16State timer[TIMER_MAX];
> +=C2=A0 =C2=A0 AVRWatchdogState wdt;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t xtal_freq_hz;
>=C2=A0 =C2=A0};
>=C2=A0 =C2=A0
> diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
> index 66e1d029e3..e0f89d2fe0 100644
> --- a/hw/watchdog/Kconfig
> +++ b/hw/watchdog/Kconfig
> @@ -20,3 +20,6 @@ config WDT_IMX2
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0config WDT_SBSA
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
> +
> +config AVR_WDT
> +=C2=A0 =C2=A0 bool
> diff --git a/hw/watchdog/avr_wdt.c b/hw/watchdog/avr_wdt.c
> new file mode 100644
> index 0000000000..4ce1029a64
> --- /dev/null
> +++ b/hw/watchdog/avr_wdt.c
> @@ -0,0 +1,190 @@
> +/*
> + * AVR watchdog
> + *
> + * Copyright (c) 2018 Michael Rolnik

2021?

> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.=
> + *
> + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the= GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html&= gt;
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +#include "hw/irq.h"
> +#include "hw/watchdog/avr_wdt.h"
> +#include "trace.h"
> +
> +/* Field masks */
> +#define WDTCSR_MASK_WDP0=C2=A0 =C2=A0 =C2=A00x01
> +#define WDTCSR_MASK_WDP1=C2=A0 =C2=A0 =C2=A00x02
> +#define WDTCSR_MASK_WDP2=C2=A0 =C2=A0 =C2=A00x04
> +#define WDTCSR_MASK_WDE=C2=A0 =C2=A0 =C2=A0 0x08
> +#define WDTCSR_MASK_WCE=C2=A0 =C2=A0 =C2=A0 0x10
> +#define WDTCSR_MASK_WDP3=C2=A0 =C2=A0 =C2=A00x20
> +#define WDTCSR_MASK_WDIE=C2=A0 =C2=A0 =C2=A00x40
> +#define WDTCSR_MASK_WDIF=C2=A0 =C2=A0 =C2=A00x80
> +
> +#define WDTCSR_SHFT_WDP0=C2=A0 =C2=A0 =C2=A00x00
> +#define WDTCSR_SHFT_WDP1=C2=A0 =C2=A0 =C2=A00x01
> +#define WDTCSR_SHFT_WDP2=C2=A0 =C2=A0 =C2=A00x02
> +#define WDTCSR_SHFT_WDE=C2=A0 =C2=A0 =C2=A0 0x03
> +#define WDTCSR_SHFT_WCE=C2=A0 =C2=A0 =C2=A0 0x04
> +#define WDTCSR_SHFT_WDP3=C2=A0 =C2=A0 =C2=A00x05
> +#define WDTCSR_SHFT_WDIE=C2=A0 =C2=A0 =C2=A00x06
> +#define WDTCSR_SHFT_WDIF=C2=A0 =C2=A0 =C2=A00x07
> +
> +/* Helper macros */
> +#define WDP0(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0((csr & WDTCSR_MASK_W= DP0) >> WDTCSR_SHFT_WDP0)
> +#define WDP1(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0((csr & WDTCSR_MASK_W= DP1) >> WDTCSR_SHFT_WDP1)
> +#define WDP2(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0((csr & WDTCSR_MASK_W= DP2) >> WDTCSR_SHFT_WDP2)
> +#define WDP3(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0((csr & WDTCSR_MASK_W= DP3) >> WDTCSR_SHFT_WDP3)
> +#define WDP(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0 ((WDP3(csr) << 3) |= (WDP2(csr) << 2) | \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0(WDP1(csr) << 1) | (WDP0(csr) << 0))
> +#define WDIE(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0((csr & WDTCSR_MASK_W= DIE) >> WDTCSR_SHFT_WDIE)
> +#define WDE(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0 ((csr & WDTCSR_MASK_W= DE) >> WDTCSR_SHFT_WDE)
> +#define WCE(csr)=C2=A0 =C2=A0 =C2=A0 =C2=A0 ((csr & WDTCSR_MASK_W= CE) >> WDTCSR_SHFT_WCE)
> +
> +#define DB_PRINT(fmt, args...) /* Nothing */
> +
> +#define MS2NS(n)=C2=A0 =C2=A0 =C2=A0 =C2=A0 ((n) * 1000000ull)
> +
> +static void avr_wdt_reset_alarm(AVRWatchdogState *wdt)
> +{
> +=C2=A0 =C2=A0 uint32_t csr =3D wdt->csr;
> +=C2=A0 =C2=A0 int wdp =3D WDP(csr);
> +=C2=A0 =C2=A0 assert(wdp <=3D 9);

Maybe qemu_log(..) instead and pick a default value?

> +
> +=C2=A0 =C2=A0 if (WDIE(csr) =3D=3D 0 && WDE(csr) =3D=3D 0) {<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* watchdog is stopped */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 timer_mod_ns(wdt->timer, qemu_clock_get_ns(QEMU_CLOC= K_VIRTUAL) +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (MS2NS(15) << wdp));<= br> > +}
> +
> +static void avr_wdt_interrupt(void *opaque)
> +{
> +=C2=A0 =C2=A0 AVRWatchdogState *wdt =3D opaque;
> +=C2=A0 =C2=A0 int8_t csr =3D wdt->csr;
> +
> +=C2=A0 =C2=A0 if (WDE(csr) =3D=3D 0 && WDIE(csr) =3D=3D 0) {<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Stopped */
> +
> +=C2=A0 =C2=A0 } else if (WDE(csr) =3D=3D 0 && WDIE(csr) =3D= =3D 1) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Interrupt Mode */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 wdt->csr |=3D WDTCSR_MASK_WDIF;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_set_irq(wdt->irq, 1);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_avr_wdt_interrupt();
> +=C2=A0 =C2=A0 } else if (WDE(csr) =3D=3D 1 && WDIE(csr) =3D= =3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* System Reset Mode */

=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_= RESET);

+/- setting the MCUSR, WDRF flags would be nice.

> +=C2=A0 =C2=A0 } else if (WDE(csr) =3D=3D 1 && WDIE(csr) =3D= =3D 1) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Interrupt and System Reset Mode */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 wdt->csr |=3D WDTCSR_MASK_WDIF;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_set_irq(wdt->irq, 1);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_avr_wdt_interrupt();
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 avr_wdt_reset_alarm(wdt);
> +}
> +
> +static void avr_wdt_reset(DeviceState *dev)
> +{
> +=C2=A0 =C2=A0 AVRWatchdogState *wdt =3D AVR_WDT(dev);
> +
> +=C2=A0 =C2=A0 wdt->csr =3D 0;
> +=C2=A0 =C2=A0 qemu_set_irq(wdt->irq, 0);
> +=C2=A0 =C2=A0 avr_wdt_reset_alarm(wdt);
> +}
> +
> +static uint64_t avr_wdt_read(void *opaque, hwaddr offset, unsigned si= ze)
> +{
> +=C2=A0 =C2=A0 assert(size =3D=3D 1);
> +=C2=A0 =C2=A0 AVRWatchdogState *wdt =3D opaque;
> +=C2=A0 =C2=A0 uint8_t retval =3D wdt->csr;
> +
> +=C2=A0 =C2=A0 trace_avr_wdt_read(offset, retval);
> +
> +=C2=A0 =C2=A0 return (uint64_t)retval;
> +}
> +
> +static void avr_wdt_write(void *opaque, hwaddr offset,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t val64, unsigned size)
> +{
> +=C2=A0 =C2=A0 assert(size =3D=3D 1);
> +=C2=A0 =C2=A0 AVRWatchdogState *wdt =3D opaque;
> +=C2=A0 =C2=A0 uint8_t val8 =3D (uint8_t)val64;
> +
> +=C2=A0 =C2=A0 trace_avr_wdt_write(offset, val8);
> +
> +=C2=A0 =C2=A0 wdt->csr =3D val8;
> +=C2=A0 =C2=A0 avr_wdt_reset_alarm(wdt);
> +}
> +
> +static const MemoryRegionOps avr_wdt_ops =3D {
> +=C2=A0 =C2=A0 .read =3D avr_wdt_read,
> +=C2=A0 =C2=A0 .write =3D avr_wdt_write,
> +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
> +=C2=A0 =C2=A0 .impl =3D {.max_access_size =3D 1}
> +};
> +
> +static void avr_wdt_wdr(void *opaque, int irq, int level)
> +{
> +=C2=A0 =C2=A0 AVRWatchdogState *wdt =3D AVR_WDT(opaque);
> +
> +=C2=A0 =C2=A0 avr_wdt_reset_alarm(wdt);
> +}
> +
> +static void avr_wdt_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 AVRWatchdogState *s =3D AVR_WDT(obj);
> +
> +=C2=A0 =C2=A0 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); > +
> +=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, obj, &avr_w= dt_ops,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 s, "avr-wdt", 0xa);
> +
> +=C2=A0 =C2=A0 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem)= ;
> +=C2=A0 =C2=A0 qdev_init_gpio_in_named(DEVICE(s), avr_wdt_wdr, "w= dr", 1);
> +}
> +
> +static void avr_wdt_realize(DeviceState *dev, Error **errp)
> +{
> +=C2=A0 =C2=A0 AVRWatchdogState *s =3D AVR_WDT(dev);
> +
> +=C2=A0 =C2=A0 s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_wd= t_interrupt, s);
> +}
> +
> +static void avr_wdt_class_init(ObjectClass *klass, void *data)
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
> +
> +=C2=A0 =C2=A0 dc->reset =3D avr_wdt_reset;
> +=C2=A0 =C2=A0 dc->realize =3D avr_wdt_realize;
> +}
> +
> +static const TypeInfo avr_wdt_info =3D {
> +=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AVR_WD= T,
> +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEV= ICE,
> +=C2=A0 =C2=A0 .instance_size =3D sizeof(AVRWatchdogState),
> +=C2=A0 =C2=A0 .instance_init =3D avr_wdt_init,
> +=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D avr_wdt_class_init,
> +};
> +
> +static void avr_wdt_register_types(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&avr_wdt_info);
> +}
> +
> +type_init(avr_wdt_register_types)
> diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build
> index 054c403dea..8db2be8317 100644
> --- a/hw/watchdog/meson.build
> +++ b/hw/watchdog/meson.build
> @@ -6,3 +6,5 @@ softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_= true: files('wdt_diag288.c'))
>=C2=A0 =C2=A0softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true:= files('wdt_aspeed.c'))
>=C2=A0 =C2=A0softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: f= iles('wdt_imx2.c'))
>=C2=A0 =C2=A0softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: f= iles('sbsa_gwdt.c'))
> +
> +specific_ss.add(when: 'CONFIG_AVR_WDT', if_true: files('a= vr_wdt.c'))
> diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
> index 3124ca1f1b..ac14773179 100644
> --- a/hw/watchdog/trace-events
> +++ b/hw/watchdog/trace-events
> @@ -5,3 +5,8 @@ cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data= , unsigned size) "CMSDK AP
>=C2=A0 =C2=A0cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, u= nsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 "= ; data 0x%" PRIx64 " size %u"
>=C2=A0 =C2=A0cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: r= eset"
>=C2=A0 =C2=A0cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB wat= chdog: lock %" PRIu32
> +
> +# avr_wdt.c
> +avr_wdt_read(uint8_t addr, uint8_t value) "wdt read addr:%u valu= e:%u"
> +avr_wdt_write(uint8_t addr, uint8_t value) "wdt write addr:%u va= lue:%u"
> +avr_wdt_interrupt(void) ""
> diff --git a/include/hw/watchdog/avr_wdt.h b/include/hw/watchdog/avr_w= dt.h
> new file mode 100644
> index 0000000000..2679e8f2a6
> --- /dev/null
> +++ b/include/hw/watchdog/avr_wdt.h
> @@ -0,0 +1,47 @@
> +/*
> + * AVR 16-bit timer

AVR Watchdog?

> + *
> + * Copyright (c) 2021 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.=
> + *
> + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the= GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html&= gt;
> + */
> +
> +#ifndef HW_WATCHDOG_AVR_WDT_H
> +#define HW_WATCHDOG_AVR_WDT_H
> +
> +#include "hw/sysbus.h"
> +#include "qemu/timer.h"
> +#include "hw/hw.h"
> +#include "qom/object.h"
> +
> +#define TYPE_AVR_WDT "avr-wdt"
> +OBJECT_DECLARE_SIMPLE_TYPE(AVRWatchdogState, AVR_WDT)
> +
> +struct AVRWatchdogState {
> +=C2=A0 =C2=A0 /* <private> */
> +=C2=A0 =C2=A0 SysBusDevice parent_obj;
> +
> +=C2=A0 =C2=A0 /* <public> */
> +=C2=A0 =C2=A0 MemoryRegion iomem;
> +=C2=A0 =C2=A0 MemoryRegion imsk_iomem;
> +=C2=A0 =C2=A0 MemoryRegion ifr_iomem;
> +=C2=A0 =C2=A0 QEMUTimer *timer;
> +=C2=A0 =C2=A0 qemu_irq irq;
> +
> +=C2=A0 =C2=A0 /* registers */
> +=C2=A0 =C2=A0 uint8_t csr;
> +};
> +
> +#endif /* HW_WATCHDOG_AVR_WDT_H */
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index 0f4596932b..d5eb785833 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -131,6 +131,9 @@ static void avr_cpu_initfn(Object *obj)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Set the number of interrupts supported by= the CPU. */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_i= nt,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0sizeof(cpu->env.intsrc) * 8);
> +
> +=C2=A0 =C2=A0 /* register watchdog timer reset interrupt */
> +=C2=A0 =C2=A0 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->wdr,= "wdr", 1);
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0static ObjectClass *avr_cpu_class_by_name(const char *cpu_= model)
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> index d148e8c75a..f8f5641c8b 100644
> --- a/target/avr/cpu.h
> +++ b/target/avr/cpu.h
> @@ -152,6 +152,7 @@ typedef struct AVRCPU {
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0CPUNegativeOffsetState neg;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0CPUAVRState env;
> +=C2=A0 =C2=A0 qemu_irq wdr; /* reset WDT */
>=C2=A0 =C2=A0} AVRCPU;
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0extern const struct VMStateDescription vms_avr_cpu;
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index 35e1019594..dd88057e5f 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -24,6 +24,7 @@
>=C2=A0 =C2=A0#include "exec/exec-all.h"
>=C2=A0 =C2=A0#include "exec/address-spaces.h"
>=C2=A0 =C2=A0#include "exec/helper-proto.h"
> +#include "hw/irq.h"
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_re= quest)
>=C2=A0 =C2=A0{
> @@ -188,11 +189,9 @@ void helper_break(CPUAVRState *env)
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0void helper_wdr(CPUAVRState *env)
>=C2=A0 =C2=A0{
> -=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
> +=C2=A0 =C2=A0 AVRCPU *cpu =3D env_archcpu(env);
>=C2=A0 =C2=A0
> -=C2=A0 =C2=A0 /* WD is not implemented yet, placeholder */
> -=C2=A0 =C2=A0 cs->exception_index =3D EXCP_DEBUG;
> -=C2=A0 =C2=A0 cpu_loop_exit(cs);
> +=C2=A0 =C2=A0 qemu_set_irq(cpu->wdr, 1);
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0/*
>

Thanks!


--
Best Regards,
Michael Rolnik


--
Best Regards,
Michael Rolnik
--0000000000000a510f05c17288e0--