From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sachin Kamat Subject: Re: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock Date: Thu, 19 Jun 2014 11:35:12 +0530 Message-ID: References: <1403156836-24421-1-git-send-email-rahul.sharma@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1403156836-24421-1-git-send-email-rahul.sharma@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org To: Rahul Sharma Cc: linux-samsung-soc , devicetree@vger.kernel.org, "linux-arm-kernel@lists.infradead.org" , mturquette@linaro.org, Tomasz Figa , Kukjin Kim , joshi@samsung.com, r.sh.open@gmail.com List-Id: devicetree@vger.kernel.org On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma wrote: > Change bit from 2 to 9 for tv (mixer) sysmmu clock. > > Signed-off-by: Rahul Sharma > --- > Based on Kukjin's for-next branch. > > drivers/clk/samsung/clk-exynos5250.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c > index 1fad4c5..184f642 100644 > --- a/drivers/clk/samsung/clk-exynos5250.c > +++ b/drivers/clk/samsung/clk-exynos5250.c > @@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { > GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), > GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), > GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", > - GATE_IP_DISP1, 2, 0, 0), > + GATE_IP_DISP1, 9, 0, 0), SysMMU TV corresponds to bit 9 as per user manual of 5250. Reviewed-by: Sachin Kamat From mboxrd@z Thu Jan 1 00:00:00 1970 From: sachin.kamat@samsung.com (Sachin Kamat) Date: Thu, 19 Jun 2014 11:35:12 +0530 Subject: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock In-Reply-To: <1403156836-24421-1-git-send-email-rahul.sharma@samsung.com> References: <1403156836-24421-1-git-send-email-rahul.sharma@samsung.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma wrote: > Change bit from 2 to 9 for tv (mixer) sysmmu clock. > > Signed-off-by: Rahul Sharma > --- > Based on Kukjin's for-next branch. > > drivers/clk/samsung/clk-exynos5250.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c > index 1fad4c5..184f642 100644 > --- a/drivers/clk/samsung/clk-exynos5250.c > +++ b/drivers/clk/samsung/clk-exynos5250.c > @@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { > GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), > GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), > GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", > - GATE_IP_DISP1, 2, 0, 0), > + GATE_IP_DISP1, 9, 0, 0), SysMMU TV corresponds to bit 9 as per user manual of 5250. Reviewed-by: Sachin Kamat