From mboxrd@z Thu Jan 1 00:00:00 1970 From: Masahiro Yamada Date: Fri, 10 Jan 2020 11:45:18 +0900 Subject: [PATCH 1/3] mtd: rawnand: denali-spl: Add missing hardware init In-Reply-To: <20200110001417.82917-1-marex@denx.de> References: <20200110001417.82917-1-marex@denx.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote: > > While the Denali NAND is initialized by the BootROM in SPL, there > are still a couple of settings which are missing. This statement is wrong. While the Denali NAND is initialized by the BootROM, the SOCFPGA SPL calls socfpga_per_reset_all() to put most of peripherals into the reset state. So, all the register values are lost. > These can trigger > subtle corruption of the data read out of the NAND. Fill these > settings in just like they are filled in by the full Denali NAND > driver in denali_hw_init(). > > Signed-off-by: Marek Vasut > Cc: Masahiro Yamada > --- > drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c > index dbaba3cab2..b8b29812aa 100644 > --- a/drivers/mtd/nand/raw/denali_spl.c > +++ b/drivers/mtd/nand/raw/denali_spl.c > @@ -173,6 +173,13 @@ void nand_init(void) > page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); > oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); > pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); > + > + /* Do as denali_hw_init() does. */ > + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, > + denali_flash_reg + SPARE_AREA_SKIP_BYTES); > + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); > + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); > + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); You put this code just because you found it worked for your board. If you reset the NAND controller, not only these four, but all the register values are lost. Especially, page_size, oob_size, etc. https://github.com/u-boot/u-boot/blob/v2020.01/drivers/mtd/nand/raw/denali_spl.c#L170 It is working on your board because SOCFPGA enables the reset sequencer, which enumerates the nand chip by hardware. It is not necessarily true for other platforms, like the UniPhier platform. The reliable way for full initialization is to call nand_scan_ident(), which is too big for SPL. To sum up, this is not a proper approach. Do not reset the NAND controller in SPL. Keep the working state that has already been set up by the boot ROM. > } > > int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) > -- > 2.24.1 > -- Best Regards Masahiro Yamada