From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89778C433E9 for ; Tue, 12 Jan 2021 08:47:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D06E22E00 for ; Tue, 12 Jan 2021 08:47:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392401AbhALIrC (ORCPT ); Tue, 12 Jan 2021 03:47:02 -0500 Received: from mail.kernel.org ([198.145.29.99]:55008 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727057AbhALIrC (ORCPT ); Tue, 12 Jan 2021 03:47:02 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 130D022E01; Tue, 12 Jan 2021 08:46:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610441181; bh=Y1GzYRbQvrAPA/+w1mjAvZdM3kH7poVhJbFhssGvWnw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=EwRH1UUigmJkvLWs0zORnRvjcjGyy3vuh0jpp1r1H5YX2E522bpGtszkvGKx64m3X Ymz/Q234SAv+7joy2teL8vX4xwjk4QDTsTjI3+D2AtLq+uts/A7DzkUPr7o2vmR99A L5AN+fNkQ86GxcpqFSuGY4UftH0A+zK4E9XKCrYQZc6Lab7p0umIx8AWZcNwJXraPN RQu6dHjhQT6otREr4uaNIkylbzTBrTrppJ5LobR7uSzuSa+UEZsuR/YeQwXpJAvYei HedUcDEu53rfEX9lCcs6RIrEvAwB+G+KrMf/0ldyvCyDw4kV6/D/1AFvFZRnm0RjR8 +6ySg8ygZjWjQ== Received: by mail-ot1-f42.google.com with SMTP id i6so1587325otr.2; Tue, 12 Jan 2021 00:46:21 -0800 (PST) X-Gm-Message-State: AOAM530oZ/ijjpN2jx8H2PsvHXy+dEB+xZR5N5+mNKMpASQZTN1kV6CM xLlZoOzJCESBrQGFqwY0bPTRQ4RJDEGU1iEpfRo= X-Google-Smtp-Source: ABdhPJzM9ncpX519OYLH+0PC8S0hC9gQaClB61ZqP0E18csMrNH++9ADD1MzAIeMYrL667BHTQMz5f0adu6PvVREwuE= X-Received: by 2002:a05:6830:2413:: with SMTP id j19mr2191096ots.251.1610441180241; Tue, 12 Jan 2021 00:46:20 -0800 (PST) MIME-Version: 1.0 References: <20210112015602.497-1-thunder.leizhen@huawei.com> <20210112015602.497-3-thunder.leizhen@huawei.com> In-Reply-To: <20210112015602.497-3-thunder.leizhen@huawei.com> From: Arnd Bergmann Date: Tue, 12 Jan 2021 09:46:03 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller To: Zhen Lei Cc: Russell King , Greg Kroah-Hartman , Will Deacon , Haojian Zhuang , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei wrote: > +--- > +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon L3 cache controller > + > +maintainers: > + - Wei Xu > + > +description: | > + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical > + addresses. The data cached in the L3 outer cache can be operated based on the > + physical address range or the entire cache. > + > +properties: > + compatible: > + items: > + - const: hisilicon,l3cache > + The compatible string needs to be a little more specific, I'm sure you cannot guarantee that this is the only L3 cache controller ever designed in the past or future by HiSilicon. Normally when you have an IP block that is itself unnamed but that is specific to one or a few SoCs but that has no na, the convention is to include the name of the first SoC that contained it. Can you share which products actually use this L3 cache controller? On a related note, what does the memory map look like on this chip? Do you support more than 4GB of total installed memory? If you do, this becomes a problem in the future as highmem support winds down. In fact anything more than 1GB on a 32-bit system requires more work on the kernel to be completed before we remove highmem, and will incur a slowdown. If the total is under 4GB but the memory is not in a contiguous physical address range. See my Linaro connect presentation[1] for further information on the topic. Arnd [1] https://connect.linaro.org/resources/lvc20/lvc20-106/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B723CC433E0 for ; Tue, 12 Jan 2021 08:47:54 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 573C922D58 for ; Tue, 12 Jan 2021 08:47:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 573C922D58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:In-Reply-To: References:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wrPz/3VXMPuWmELq/95RlytpJftRqKw6ti9vRPgpngc=; b=rtPOYk9oxFOF7l3G7ioLrw0W5 lDTfzUXZil/+92rHe3cDDKhab9uXJjMhzAuZ6vcHHAekOy+++w9B+Mwd3RTyRFEGuV5yDowoba8cW TF0XXUeHazUJ82EDQ2ysynC1t7uYYdxHO4BWD8WAQC3G+wT6Tt3wMdbLfVJHFS81DBifaf7S9keLg sK2cYpRWFdR08jp+YwvEPaUWj1+JNmGMlNAFGPOwaJIbzjU5coXP7DHknEN3EXN5/nWTvH6mvPnDJ +i/unKG26W0K7zXhtSGyvWyrw6Z/dmzSlzNj+6q8bGzzlvKXXDQr4XScOo1F+EwiQF/6qczqyLdn4 LIMZWsRcw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kzFJs-0001Uo-Bq; Tue, 12 Jan 2021 08:46:28 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kzFJl-0001TO-UT for linux-arm-kernel@lists.infradead.org; Tue, 12 Jan 2021 08:46:23 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1C3AE22E03 for ; Tue, 12 Jan 2021 08:46:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610441181; bh=Y1GzYRbQvrAPA/+w1mjAvZdM3kH7poVhJbFhssGvWnw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=EwRH1UUigmJkvLWs0zORnRvjcjGyy3vuh0jpp1r1H5YX2E522bpGtszkvGKx64m3X Ymz/Q234SAv+7joy2teL8vX4xwjk4QDTsTjI3+D2AtLq+uts/A7DzkUPr7o2vmR99A L5AN+fNkQ86GxcpqFSuGY4UftH0A+zK4E9XKCrYQZc6Lab7p0umIx8AWZcNwJXraPN RQu6dHjhQT6otREr4uaNIkylbzTBrTrppJ5LobR7uSzuSa+UEZsuR/YeQwXpJAvYei HedUcDEu53rfEX9lCcs6RIrEvAwB+G+KrMf/0ldyvCyDw4kV6/D/1AFvFZRnm0RjR8 +6ySg8ygZjWjQ== Received: by mail-ot1-f47.google.com with SMTP id q25so1540443otn.10 for ; Tue, 12 Jan 2021 00:46:21 -0800 (PST) X-Gm-Message-State: AOAM531DrLKJbS3i7GmcpQFlWVeR80vQ5LJpLVZFUbNMWyiqgNnomUJR oFHo4WGkthX0Jb2+dsb9HStlvmullJSpMtolejA= X-Google-Smtp-Source: ABdhPJzM9ncpX519OYLH+0PC8S0hC9gQaClB61ZqP0E18csMrNH++9ADD1MzAIeMYrL667BHTQMz5f0adu6PvVREwuE= X-Received: by 2002:a05:6830:2413:: with SMTP id j19mr2191096ots.251.1610441180241; Tue, 12 Jan 2021 00:46:20 -0800 (PST) MIME-Version: 1.0 References: <20210112015602.497-1-thunder.leizhen@huawei.com> <20210112015602.497-3-thunder.leizhen@huawei.com> In-Reply-To: <20210112015602.497-3-thunder.leizhen@huawei.com> From: Arnd Bergmann Date: Tue, 12 Jan 2021 09:46:03 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller To: Zhen Lei X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210112_034622_125032_285E57FA X-CRM114-Status: GOOD ( 16.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , Arnd Bergmann , Greg Kroah-Hartman , Will Deacon , linux-kernel , Haojian Zhuang , Rob Herring , Wei Xu , Russell King , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei wrote: > +--- > +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon L3 cache controller > + > +maintainers: > + - Wei Xu > + > +description: | > + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical > + addresses. The data cached in the L3 outer cache can be operated based on the > + physical address range or the entire cache. > + > +properties: > + compatible: > + items: > + - const: hisilicon,l3cache > + The compatible string needs to be a little more specific, I'm sure you cannot guarantee that this is the only L3 cache controller ever designed in the past or future by HiSilicon. Normally when you have an IP block that is itself unnamed but that is specific to one or a few SoCs but that has no na, the convention is to include the name of the first SoC that contained it. Can you share which products actually use this L3 cache controller? On a related note, what does the memory map look like on this chip? Do you support more than 4GB of total installed memory? If you do, this becomes a problem in the future as highmem support winds down. In fact anything more than 1GB on a 32-bit system requires more work on the kernel to be completed before we remove highmem, and will incur a slowdown. If the total is under 4GB but the memory is not in a contiguous physical address range. See my Linaro connect presentation[1] for further information on the topic. Arnd [1] https://connect.linaro.org/resources/lvc20/lvc20-106/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel