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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=RqspwjyWW5d1MpGjILadsGerXh6vodVcZI2gsZCaqdo=; b=PQh8vKlK8HrIGIAbV3Dq2F+0e/D5FWC1vVaoSJ+afu85P3S9jZRWVMmINUOBS0wH0T efIJ6anqKQB9BCeyXXhinelaQEk/+R3/I50YB3YUVBWsQ3NR6NJgaMT3ges2FHA2YR84 Q6PWId5MH1Sw4lu2vOZ+JcoYPj68/0kgJ5KtnqxOZtCu+K4XLPz+yLYSYCfEnYXQ2EEL KyJwvWPqXPCynaTxKGI78Wseq6Q1vZxpGrckWOnghdmfFis/YVewbgX2v/JtSIIrjILb mhh+jVRJNO8eTtNLCsnUxbuynoFpeEUtMxQxmT5q52wkGdG2mHBoIKdJwkDMj5S3ZtbN DQoA== X-Gm-Message-State: APt69E23kx73r+t4+j1Nb+0L9uL1XdK6MfQy8fuIOAqB2xDqVgj7AN7N 38qMPY1eWYnpOIw0/D/eGx9N7BGbGOTgfHMELwc= X-Google-Smtp-Source: ADUXVKJMgXWeh9+X3zdwaoqccLsssoMFt3j5Ctj5FUgJ+S8iT4cxXMrzFCdABOQeiAxdDbuXFhWUd8ONOdKjMqYKfaA= X-Received: by 2002:a2e:40d9:: with SMTP id r86-v6mr7852423lje.19.1529319565609; Mon, 18 Jun 2018 03:59:25 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a2e:56c8:0:0:0:0:0 with HTTP; Mon, 18 Jun 2018 03:59:24 -0700 (PDT) In-Reply-To: <539411c1-82b7-cf76-71cf-d50f3303f50f@linux.intel.com> References: <20180612054034.4969-1-songjun.wu@linux.intel.com> <20180612054034.4969-2-songjun.wu@linux.intel.com> <539411c1-82b7-cf76-71cf-d50f3303f50f@linux.intel.com> From: Arnd Bergmann Date: Mon, 18 Jun 2018 12:59:24 +0200 X-Google-Sender-Auth: gu4KI2rTFfqxs5zpg0x6cE7uD9o Message-ID: Subject: Re: [PATCH 1/7] MIPS: dts: Add aliases node for lantiq danube serial To: "Wu, Songjun" Cc: hua.ma@linux.intel.com, yixin.zhu@linux.intel.com, chuanhua.lei@intel.com, "open list:RALINK MIPS ARCHITECTURE" , qi-ming.wu@intel.com, linux-clk , linux-serial@vger.kernel.org, DTML , James Hogan , Linux Kernel Mailing List , Thomas Gleixner , Philippe Ombredanne , Rob Herring , Kate Stewart , Greg Kroah-Hartman , Mark Rutland , Ralf Baechle Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 18, 2018 at 11:42 AM, Wu, Songjun wrote: > On 6/14/2018 6:03 PM, Arnd Bergmann wrote: >> >> On Tue, Jun 12, 2018 at 7:40 AM, Songjun Wu >> wrote: >>> >>> Previous implementation uses a hard-coded register value to check if >>> the current serial entity is the console entity. >>> Now the lantiq serial driver uses the aliases for the index of the >>> serial port. >>> The lantiq danube serial dts are updated with aliases to support this. >>> >>> Signed-off-by: Songjun Wu >>> --- >>> >>> arch/mips/boot/dts/lantiq/danube.dtsi | 6 +++++- >>> 1 file changed, 5 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi >>> b/arch/mips/boot/dts/lantiq/danube.dtsi >>> index 2dd950181f8a..7a9e15da6bd0 100644 >>> --- a/arch/mips/boot/dts/lantiq/danube.dtsi >>> +++ b/arch/mips/boot/dts/lantiq/danube.dtsi >>> @@ -4,6 +4,10 @@ >>> #size-cells = <1>; >>> compatible = "lantiq,xway", "lantiq,danube"; >>> >>> + aliases { >>> + serial0 = &asc1; >>> + }; >>> + >> >> You generally want the aliases to be part of the board specific file, >> not every board numbers their serial ports in the same way. >> > > In this chip only asc1 can be used as console, so serial0 is defined in > chip specific file. This was a more general comment about 'aliases' being board specific in principle (though we've had exceptions in the past). Even if there is only one uart on the chip, I'd recommend following the same conventions as the other chips that have more than one uart. Arnd