Re: [PATCH 04/17 v1] irqchip: Add driver for IXP4xx

From: Arnd Bergmann <arnd@arndb.de>
To: "Krzysztof Hałasa" <khalasa@piap.pl>
Cc: Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Olof Johansson <olof@lixom.net>,
	Thomas Gleixner <tglx@linutronix.de>,
	Imre Kaloz <kaloz@openwrt.org>,
	Tim Harvey <tharvey@gateworks.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 04/17 v1] irqchip: Add driver for IXP4xx
Date: Tue, 19 Feb 2019 10:46:47 +0100	[thread overview]
Message-ID: <CAK8P3a10daNVCMOSKcLTG=0-YkK4sQ0p3Uu-wM3xM5TEimUzkQ@mail.gmail.com> (raw)
In-Reply-To: <m37edwuv8m.fsf@t19.piap.pl>

On Tue, Feb 19, 2019 at 7:51 AM Krzysztof Hałasa <khalasa@piap.pl> wrote:
> Arnd Bergmann <arnd@arndb.de> writes:
> > - I have a vague memory that only specific revisions actually require
> >   the PCI indirect mode. Is it the same chip revision A0 of IXP425
> >   that requires both pci-indirect and address-coherent mode, or are
> >   there other combinations?
>
> IIRC, all chips support indirect PCI. Perhaps there are some changes
> about LE mode on the PCI, but that's it.
>
> Most boards don't need indirect PCI. It's only needed when there is more
> than 64 MB of PCI address space to be used - IIRC IXP4xx have 4 direct
> PCI memory access windows, and each is 16 MB in size.
> I remember I needed indirect PCI for use with a (SiS?) VGA card, it had
> (I guess) 128 MB of RAM. I think indirect PCI means the memory can't be
> really mapped, it can only be accessed using readl() and friends (which
> are then converted into register accesses resulting in the actual MMIO).
> Even with indirect PCI, 64 MB can be accessed directly (though I think
> we don't support it).
>
> This is different from the bus mastering access to the main RAM - I
> think only the first 64 MB can be used for PCI BM DMA. This limitation,
> IIRC, doesn't apply to internal devices (Ethernet etc).

Thanks a lot for this background, that helps a lot. We actually
have a more general implementation of this (indirect mmio and pio)
in arch/powerpc/kernel/io-workarounds.c, and I was considering
whether we can make that architecture independent code and
reuse it here as well.

Looking at the powerpc implementation however, I see two other
problems:

- the way it is implemented requires using some spare address
  bits on a 64-bit pointer, so that would have to be change a lot
  to work on a 32-bit architecture
- the MMIO workarounds don't really work for a VGA card
  in general since you cannot map the frame buffer into user
  space, so the application of that is still a bit limited. I suspect
  you would have had the same problem with the existing
  ixp4xx code as well, depending on how the driver implements
  user space graphics.

We could still consider using it on Allwinner H6, which is a 64-bit
chip that is even more limited (only 64 /KB/ can be mapped at a
time).

> > - How much would it hurt actual users to drop support for both
> >   features? I.e. do we know of anyone using the affected chips
> >   (and still doing updates), or are the remaining ixp4xx systems
> >   generally using the later chip revision?
>
> Most chips are B0+, though there are (were) certain A0 platforms.
> I don't have any idea about their current use.

Ok, fair enough.

     Arnd

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