From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 357F2C4338F for ; Wed, 18 Aug 2021 09:38:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1842860F39 for ; Wed, 18 Aug 2021 09:38:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232918AbhHRJjW (ORCPT ); Wed, 18 Aug 2021 05:39:22 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:60275 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233749AbhHRJjS (ORCPT ); Wed, 18 Aug 2021 05:39:18 -0400 Received: from mail-wr1-f53.google.com ([209.85.221.53]) by mrelayeu.kundenserver.de (mreue011 [213.165.67.97]) with ESMTPSA (Nemesis) id 1N2Dks-1nCyHk23jC-013cPv for ; Wed, 18 Aug 2021 11:38:42 +0200 Received: by mail-wr1-f53.google.com with SMTP id q10so2504038wro.2 for ; Wed, 18 Aug 2021 02:38:42 -0700 (PDT) X-Gm-Message-State: AOAM531uJ/I4WMSj/C4i260T9MwRkVMceglZK1dgIqZBbHV3JVU/E+Wi uAjlodvWUDnGW9BzBcBU10AfZA2C8D5teaPJGrk= X-Google-Smtp-Source: ABdhPJxTxHKAX2unhNHO4ybczrtTqS8ClS+7dRKaPktGvZzqdahQsYngyAclCyCQVblExLoPyxheh+ix56DRPtx/A14= X-Received: by 2002:adf:f202:: with SMTP id p2mr9695041wro.361.1629279522052; Wed, 18 Aug 2021 02:38:42 -0700 (PDT) MIME-Version: 1.0 References: <20210706041820.1536502-1-chenhuacai@loongson.cn> <20210706041820.1536502-5-chenhuacai@loongson.cn> In-Reply-To: From: Arnd Bergmann Date: Wed, 18 Aug 2021 11:38:26 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 04/19] LoongArch: Add common headers To: Huacai Chen Cc: Arnd Bergmann , Huacai Chen , Andy Lutomirski , Thomas Gleixner , Peter Zijlstra , Andrew Morton , David Airlie , Linus Torvalds , linux-arch , Xuefeng Li , Jiaxun Yang Content-Type: text/plain; charset="UTF-8" X-Provags-ID: V03:K1:ZJyMxdHY1g5L3I0L876tvgS1zc7ZDg/MEq2fwD2/Sr/WTQfj8pu 64YG1Eq73pE73eVzS9q7gaPy/7rg86V3VECYFGH7kuixIrwwnekTnDvDXkNKYb+BbPsZs/9 W18T8PlISjQZLfXEoujlcTWPvXcbK160g/EHagZUm8kf7tYGih7sLTpNSsgvzPHFVzKclVt xXzOFIWHAk13br9hrU7VA== X-UI-Out-Filterresults: notjunk:1;V03:K0:jndulHgmzOg=:/A/Id6DEoabe5RbgaTkFoU QsfutYGuofX3U2UZ9+2FuWP9EwdJTHcguoTOsLLwAS2Rwa6dvu6U2BqrpgeY2nEdHBMGa/qzQ yyHqZSH6raDLMzaNvD6PeHzDnVD0go9v2IkQMGlAnMXZeX8ny1GY+bMftlI6MXj6FdHYQilv7 YM7q+CZDm70jLqcc3AubaLx82r+SZqW/fUFxnfniPqN9apQ6iURwAzJxa33EXTQicXVDltbb+ f18rhIE76OJvibK4t3tmPRy3qBR78YgNL4jQGMfXRK7NxLwgnDeBpofAdfOkBOAKp+RNtA8f6 I1hMEqqzT4eOxlpP7p6NcMW5gMSreIXblWMrfVR0pfuhLjtx2/bfZkoyM+K8vj2SCAL+lZjYo Wejuu053nlhSJwVFruxsRgZ/yLBMXHZO6Y31F70x2V4EUNDzcl+V7errDsD1i3dwp4y06All2 Y/9BDTWuxvf3l6o4aBFeXxgDCyiP2A0aXj5BaueMzJQ+ht18INDrWPSqfyHNOXr5ixXwn2Q3h bpW3mXfMCKOKJvnWh0zSM8fZE76+nQQgYT+oKAjm17ZIKdvQsPIx3YDgMs3LweOypLXb5liJd RvbAGkZjRThNBZOtmkEFs6ymy2O1ywQsuYcbNx+8lANt/3LDTL15xn9Ru9w/DQ3IEBLRf3YsH DS7tE0/CcsaL9bA463hqJf5GU+8wZxUwMA1E11F3woKmevfnrscaew05U51PWeHOR1VGm7Pev oJn/RHWOyVgGTNIjmGVjd8634SmQxG/VFU/y7rlk3nZZFV2W83sVhJsQIp2VGK3xM1aZINoy5 /sqGKaZCcTiyQWNjd/7sP2spE+XBjlneqm9rcpT/SssnYZOn0OwU1+KFE5uVAW3wnquGNUtF8 BleFVY0Zr7iusM7VPo2YONeh+XcmScWqiSpmp7yq25PfXNz1e2j80MEgaGJSkZujfzY/sMS/4 6ZAc+dbhm9jM5g8Z6HeGwsi/FZGdwnIcRmTq4kcFNVEhKzUa1vsCx Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Mon, Aug 16, 2021 at 6:10 AM Huacai Chen wrote: > On Sun, Aug 15, 2021 at 4:56 PM Arnd Bergmann wrote: > > > #ifdef CONFIG_PAGE_SIZE_16KB > > > #define PGD_ORDER 0 > > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > > #define PMD_ORDER 0 > > > #define PTE_ORDER 0 > > > #endif > > > > This doesn't seem to make sense at all however: it looks like you have > > three levels of 16KB page tables, so you get 47 bits, not 40. This > > means you waste 99% of the available address space when you > > run this kernel on a CPU that is able to access the entire space. > Emm, this "waste" seems harmless. :) It's not actively harmful, just silly to offer the 4/11/11/14 option that is never the ideal choice given the alternatives of * 11/11/11/14: normal 16K 3level, but up to 47 bits if supported by CPU * 11/11/14: 16K 2level, just dropping the top level for 36-bit TASK_SIZE * 13/13/14: 16K 2level, fewer levels with larger PGD/PMD * 10/9/9/12: normal 4K 3level, same # of levels, better memory usage > > > #ifdef CONFIG_PAGE_SIZE_64KB > > > #define PGD_ORDER 0 > > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > > #define PMD_ORDER 0 > > > #define PTE_ORDER 0 > > > #endif > > > #endif > > > > I suppose you can't ever have more than 48 bits? Otherwise this option > > would give you 55 bits of address space. > > We will have 56bits CPU in future, and then we will add a VA_BITS_56 config. Right, so same as above: why not make this VA_BITS_55 already and fall back to 40 or 48 bits on current CPUs > > > Since 40 and 48 is the most popular VABITS of LoongArch hardware, and > > > LoongArch has a software-managed TLB, it seems "define page table > > > layout depends on kernel VABITS" is more natural for LoongArch. > > > > How common are Loongarch64 CPUs that limit the virtual address space > > to 40 bits instead of the full 48 bits? What is the purpose of limiting the > > CPU this way? > We have some low-end 64bits CPU whose VA is 40bits, this can reduce > the internal address bus width, so save some hardware cost and > complexity. Ok. So I could understand making CONFIG_VA_BITS_40 hardcode the VA size at compile time, but if you always support the fallback to any size at runtime, just allow using the high addresses. Arnd