From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: RFC on writel and writel_relaxed Date: Tue, 27 Mar 2018 22:46:53 +0200 Message-ID: References: <1521854626.16434.359.camel@kernel.crashing.org> <58ce5b83f40f4775bec1be8db66adb0d@AcuMS.aculab.com> <20180326165425.GA15554@ziepe.ca> <20180326202545.GB15554@ziepe.ca> <20180326210951.GD15554@ziepe.ca> <1522101616.7364.13.camel@kernel.crashing.org> <1e077f6a-90b6-cce9-6f0f-a8c003fec850@codeaurora.org> <20180327151029.GB17494@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Sender: netdev-owner@vger.kernel.org To: Alexander Duyck Cc: Will Deacon , Sinan Kaya , Benjamin Herrenschmidt , Jason Gunthorpe , David Laight , Oliver , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , "linux-rdma@vger.kernel.org" , Alexander Duyck , "Paul E. McKenney" , "netdev@vger.kernel.org" , Linus Torvalds List-Id: linux-rdma@vger.kernel.org On Tue, Mar 27, 2018 at 9:54 PM, Arnd Bergmann wrote: > On Tue, Mar 27, 2018 at 8:54 PM, Alexander Duyck > wrote: >> On Tue, Mar 27, 2018 at 8:10 AM, Will Deacon wrote= : > > 11.10 STORE BUFFER > Intel 64 and IA-32 processors temporarily store each write (store) to > memory in a store buffer. The store buffer > improves processor performance by allowing the processor to continue > executing instructions without having to > wait until a write to memory and/or to a cache is complete. It also > allows writes to be delayed for more efficient use > of memory-access bus cycles. > In general, the existence of the store buffer is transparent to > software, even in systems that use multiple processors. > The processor ensures that write operations are always carried out in > program order. It also insures that the > contents of the store buffer are always drained to memory in the > following situations: > =E2=80=A2 When an exception or interrupt is generated. > =E2=80=A2 (P6 and more recent processor families only) When a serializing > instruction is executed. > =E2=80=A2 When an I/O instruction is executed. I guess I/O instruction is still ambiguous on x86, it may just refer to 'inb'/'outb' style instructions rather than 'mov' on a device MMIO area. Here's a link to a reply from Linus that I found on this topic: http://yarchive.net/comp/linux/write_combining.html Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 409jjs1SSYzF2C1 for ; Wed, 28 Mar 2018 07:46:56 +1100 (AEDT) Received: by mail-io0-x242.google.com with SMTP id q80so852179ioi.13 for ; Tue, 27 Mar 2018 13:46:56 -0700 (PDT) MIME-Version: 1.0 Sender: arndbergmann@gmail.com In-Reply-To: References: <1521854626.16434.359.camel@kernel.crashing.org> <58ce5b83f40f4775bec1be8db66adb0d@AcuMS.aculab.com> <20180326165425.GA15554@ziepe.ca> <20180326202545.GB15554@ziepe.ca> <20180326210951.GD15554@ziepe.ca> <1522101616.7364.13.camel@kernel.crashing.org> <1e077f6a-90b6-cce9-6f0f-a8c003fec850@codeaurora.org> <20180327151029.GB17494@arm.com> From: Arnd Bergmann Date: Tue, 27 Mar 2018 22:46:53 +0200 Message-ID: Subject: Re: RFC on writel and writel_relaxed To: Alexander Duyck Cc: Will Deacon , Sinan Kaya , Benjamin Herrenschmidt , Jason Gunthorpe , David Laight , Oliver , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , "linux-rdma@vger.kernel.org" , Alexander Duyck , "Paul E. McKenney" , "netdev@vger.kernel.org" , Linus Torvalds Content-Type: text/plain; charset="UTF-8" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Mar 27, 2018 at 9:54 PM, Arnd Bergmann wrote: > On Tue, Mar 27, 2018 at 8:54 PM, Alexander Duyck > wrote: >> On Tue, Mar 27, 2018 at 8:10 AM, Will Deacon wrote= : > > 11.10 STORE BUFFER > Intel 64 and IA-32 processors temporarily store each write (store) to > memory in a store buffer. The store buffer > improves processor performance by allowing the processor to continue > executing instructions without having to > wait until a write to memory and/or to a cache is complete. It also > allows writes to be delayed for more efficient use > of memory-access bus cycles. > In general, the existence of the store buffer is transparent to > software, even in systems that use multiple processors. > The processor ensures that write operations are always carried out in > program order. It also insures that the > contents of the store buffer are always drained to memory in the > following situations: > =E2=80=A2 When an exception or interrupt is generated. > =E2=80=A2 (P6 and more recent processor families only) When a serializing > instruction is executed. > =E2=80=A2 When an I/O instruction is executed. I guess I/O instruction is still ambiguous on x86, it may just refer to 'inb'/'outb' style instructions rather than 'mov' on a device MMIO area. Here's a link to a reply from Linus that I found on this topic: http://yarchive.net/comp/linux/write_combining.html Arnd