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Thu, 04 Mar 2021 10:58:57 +0000 Received: from mail-ot1-f41.google.com ([209.85.210.41]) by mrelayeu.kundenserver.de (mreue109 [213.165.67.113]) with ESMTPSA (Nemesis) id 1MfpGR-1lxg1W1vRp-00gIdW for ; Thu, 04 Mar 2021 11:58:47 +0100 Received: by mail-ot1-f41.google.com with SMTP id f33so26775988otf.11 for ; Thu, 04 Mar 2021 02:58:45 -0800 (PST) X-Gm-Message-State: AOAM532s6TpegTDeqpWny57n+X84rW32BkTtoGe9NqKfUO4FYa7hgyBo KqkV1l8SqKNrsKQlJZL2pdOOvNxySOkwsp0TUzY= X-Google-Smtp-Source: ABdhPJz1isN7a4ehcF9HHNeG9q7qKHd8/FFXnPMY8/CvMfpnQJJ0Yqd+ln/usQiWPlqPIG7JB8bFXpj71N5eEjpvbrc= X-Received: by 2002:a05:6830:1b65:: with SMTP id d5mr2952747ote.305.1614855524811; Thu, 04 Mar 2021 02:58:44 -0800 (PST) MIME-Version: 1.0 References: <1614764303-34903-1-git-send-email-tan.shaopeng@jp.fujitsu.com> <1614764303-34903-2-git-send-email-tan.shaopeng@jp.fujitsu.com> <20210304104650.GA20843@willie-the-truck> In-Reply-To: <20210304104650.GA20843@willie-the-truck> From: Arnd Bergmann Date: Thu, 4 Mar 2021 11:58:28 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC] soc: fujitsu: Add cache driver code To: Will Deacon List-Id: Cc: "tan.shaopeng@fujitsu.com" , Linux ARM , SoC Team , Catalin Marinas , Olof Johansson , "misono.tomohiro@fujitsu.com" , James Morse X-Provags-ID: V03:K1:EW5iZ0FeikJEWiO9h8AjuOZGbs/pYA1jHPvCEYteQE7cc9GjUBH 6zESZ/4jmEsuCogeTbSOCgi8m3sbASKewNip8tbkkZv6KefVaIAcLJA60vw5IILpip0kBlD xCQIscRq7KPjdu1DrFzQNEtUOBSmchVExrVvLarROe1Brfek/e+CCW+6yc/igolCsEk5/aO f2/5RbPVJ70SjSplcCCow== X-UI-Out-Filterresults: notjunk:1;V03:K0:cPKaIvgc7hs=:Q1/lRA3WgL5p5vyDdV/oiC DrYbYiiVf+UTpFKtZu7+mtvaU5At2mI8bhA5r666q9NMSmhOfaJU12pum+G20iysJYyaQv/YS h/AeIFOo9gQrySquRfJXkDeYQii+Zcurvt214F4miXEn098LavY8ppfcTN8Q5WSCvnYAUbegU fksYeW3rMcLhdk00+mAqW2qo5cbKARPLny+3kaJbXGJ2sE9p5cw0h5A9KnffNcDf4HQXfqwE1 lbu2ABavG+FBeljs3rtV5Kl0oVEz1DxSVxefnDSRBCbDCWPZg4hqYw785cTjh5L9FGb+N9P8u noMFBXUmLRZkjOk0WZu7sWDIXCujtECdgj3o8dQehG6VvtqDPCOlFEakkh4wmwiB8/KsZ69rg pODneQF0qo4mqgEc9ANspeJUD+TFEF2hBcZLA7bsovjVvCsWdauUM+1zwuGhf6CErv8qRgLYp xpEicAoI8HqtCY3pltFQHQWTT6bsUWj81LE2+0A5kK3IZJuDqyE+XLi2LNGQp05XrUXCAlzLX YWfLKz+tIqBHoJZvuZJ8coUG9YX+j1Jz5ng9V2YrbNMO3hvb+PlxzWpx3d4BduPsA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210304_105857_015806_625EF36F X-CRM114-Status: GOOD ( 23.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 4, 2021 at 11:46 AM Will Deacon wrote: > On Thu, Mar 04, 2021 at 10:34:43AM +0000, tan.shaopeng@fujitsu.com wrote: > > > On Wed, Mar 3, 2021 at 10:38 AM tan.shaopeng > > > wrote: > > > > + > > > > +config FUJITSU_CACHE > > > > + tristate "FUJITSU Cache Driver" > > > > + depends on ARM64_VHE || COMPILE_TEST > > > > + help > > > > + FUJITSU Cache Driver > > > > + > > > > + This driver offers cache functions for A64FX system. > > > > + Loading this cache driver, control registers will be set to enable > > > > + these functions, and advanced settings registers will be set by > > > default > > > > + values. After loading this driver, you can use the default values of > > > the > > > > + advanced settings registers or set the advanced settings registers > > > > + from EL0. Unloading this driver, control registers will be clear to > > > > + disable these functions. > > > > + When built as a module, this will be called as "fujitsu_cache". > > > > > > My feeling is that this code should be in arch/arm64/, as the cache > > > is generally considered part of the CPU, rather than part of the wider > > > SoC design, or something that can be controlled separately from the > > > core kernel and memory management code. > > > > Thanks for your advice. I also would like to hear the opinions from > > other soc&arm maintainers, and then consider whether to add this to > > arch/arm64/. > > Given that all of this is outside of the scope of the architecture, I don't > think that arch/arm64/ is the right place for it. Perhaps this would fit > into the resctrl rework that James has been doing for MPAM? Indeed, that sounds like a good starting point. I don't understand enough about either of the two to be sure, but it sounds like there is some overlap in functionality, and ideally we would have one user interface that can deal with all the hardware implementations (intel, arm, fujitsu and any future ones). Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38594C433DB for ; Thu, 4 Mar 2021 11:03:55 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 039F464F2C; Thu, 4 Mar 2021 11:03:55 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [217.72.192.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4747C64F2B; Thu, 4 Mar 2021 11:03:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4747C64F2B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arndb.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=arnd@arndb.de Received: from mail-ot1-f48.google.com ([209.85.210.48]) by mrelayeu.kundenserver.de (mreue109 [213.165.67.113]) with ESMTPSA (Nemesis) id 1N7iKq-1lmzx60tGs-014kGJ; Thu, 04 Mar 2021 11:58:46 +0100 Received: by mail-ot1-f48.google.com with SMTP id v12so25712901ott.10; Thu, 04 Mar 2021 02:58:45 -0800 (PST) X-Gm-Message-State: AOAM531zoq82CK3DvdUggcuesUskhkBY3AUM3WgGsvLuGEODnqRsDUqv jUEaYlBVqZkckk0PW5gk8PWZo8kXWZyrF+y49gg= X-Google-Smtp-Source: ABdhPJz1isN7a4ehcF9HHNeG9q7qKHd8/FFXnPMY8/CvMfpnQJJ0Yqd+ln/usQiWPlqPIG7JB8bFXpj71N5eEjpvbrc= X-Received: by 2002:a05:6830:1b65:: with SMTP id d5mr2952747ote.305.1614855524811; Thu, 04 Mar 2021 02:58:44 -0800 (PST) MIME-Version: 1.0 References: <1614764303-34903-1-git-send-email-tan.shaopeng@jp.fujitsu.com> <1614764303-34903-2-git-send-email-tan.shaopeng@jp.fujitsu.com> <20210304104650.GA20843@willie-the-truck> In-Reply-To: <20210304104650.GA20843@willie-the-truck> From: Arnd Bergmann Date: Thu, 4 Mar 2021 11:58:28 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC] soc: fujitsu: Add cache driver code To: Will Deacon List-Id: Cc: "tan.shaopeng@fujitsu.com" , Linux ARM , SoC Team , Catalin Marinas , Olof Johansson , "misono.tomohiro@fujitsu.com" , James Morse Content-Type: text/plain; charset="UTF-8" X-Provags-ID: V03:K1:vMjJJBByJFEYcTrB4A+Ex9J2uAXtawDCIdadoi5PBxegIAhUgsy Cdh6wO5iQ9br9zUmu8ZiUoNNIvz4UW2SMamN6E+HMPb60ykAfD3QZcAr6FT5KMbKu8fKH55 hblyPvse6j1baYJE/pGgzIXo+08BcL73pyjt4hXpUuxTgKe1Ufo67OiLGOMYAzSobdQJc9D quv3dn3txwEr09bgbjLHA== X-UI-Out-Filterresults: notjunk:1;V03:K0:0X8MLLaDIL0=:aXwUI2STJXMGLvPn9lmApF DCHtsq0HhNhEUHW69OUksIRAOVU8383zsv/+GHVys+zz4I7nQuXPX2sI3dilMEpDPviwv0Tx6 Qh8QTe2dy9TdfHuyBuS55F7lqz1mBmwHJ2glBeFqwFL23EYMUuA73hW1qEmbMfHLDHVpR0hv4 ON8Ch9WIL7QK/di8jZToKJnR4H6EjjTlSI7TO2kS935AW/gJd/CF+wDGlwzJfvIf1m8fFj0hZ CDSaxun7z5tvdZ5q9MEhgPtHnNwadc4gT9rMwcJ+yXlJtBEqq3msIoMg01kOtHneOQkuxVOQ9 /X7u9K6A7kI5CFGcSYIBA5NSqGQNNA39yu3JLhWkkQsm+aFlnhN/L/ofd1f5kRx70D1Zw+RLu gx1ScFQE0jw+BNBeXeXqsMlMpl0xATuPYg6ZAH8I3pCHQxdsyl8QV/Wh50NPcVr5hePQBs16y 3Y+saCUPHthJ9ttGpDJqChtCrIoc9S6GJP/byOTeuzjxAdWgtq4uEW5iviJPp5IcwgkZ+0ZqV XhuCx68cyhnW0YgCyjNL/XnTqgiPdwo50UzdfO1/teaHvMZV/55DT+OJk/8ctQG4Q== Message-ID: <20210304105828.FwNwO6lTWcYozCebZdOmL78eul6tKD-5bucD8UlK2Sk@z> On Thu, Mar 4, 2021 at 11:46 AM Will Deacon wrote: > On Thu, Mar 04, 2021 at 10:34:43AM +0000, tan.shaopeng@fujitsu.com wrote: > > > On Wed, Mar 3, 2021 at 10:38 AM tan.shaopeng > > > wrote: > > > > + > > > > +config FUJITSU_CACHE > > > > + tristate "FUJITSU Cache Driver" > > > > + depends on ARM64_VHE || COMPILE_TEST > > > > + help > > > > + FUJITSU Cache Driver > > > > + > > > > + This driver offers cache functions for A64FX system. > > > > + Loading this cache driver, control registers will be set to enable > > > > + these functions, and advanced settings registers will be set by > > > default > > > > + values. After loading this driver, you can use the default values of > > > the > > > > + advanced settings registers or set the advanced settings registers > > > > + from EL0. Unloading this driver, control registers will be clear to > > > > + disable these functions. > > > > + When built as a module, this will be called as "fujitsu_cache". > > > > > > My feeling is that this code should be in arch/arm64/, as the cache > > > is generally considered part of the CPU, rather than part of the wider > > > SoC design, or something that can be controlled separately from the > > > core kernel and memory management code. > > > > Thanks for your advice. I also would like to hear the opinions from > > other soc&arm maintainers, and then consider whether to add this to > > arch/arm64/. > > Given that all of this is outside of the scope of the architecture, I don't > think that arch/arm64/ is the right place for it. Perhaps this would fit > into the resctrl rework that James has been doing for MPAM? Indeed, that sounds like a good starting point. I don't understand enough about either of the two to be sure, but it sounds like there is some overlap in functionality, and ideally we would have one user interface that can deal with all the hardware implementations (intel, arm, fujitsu and any future ones). Arnd