From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Cyrus-Session-Id: sloti22d1t05-4031207-1516373564-2-15336474203319115755 X-Sieve: CMU Sieve 3.0 X-Spam-known-sender: no X-Spam-score: 0.0 X-Spam-hits: BAYES_00 -1.9, FREEMAIL_FORGED_FROMDOMAIN 0.25, FREEMAIL_FROM 0.001, HEADER_FROM_DIFFERENT_DOMAINS 0.25, RCVD_IN_DNSWL_NONE -0.0001, RCVD_IN_MSPIKE_H3 -0.01, RCVD_IN_MSPIKE_WL -0.01, SPF_PASS -0.001, LANGUAGES en, BAYES_USED global, SA_VERSION 3.4.0 X-Spam-source: IP='209.85.218.66', Host='mail-oi0-f66.google.com', Country='US', FromHeader='de', MailFrom='com' X-Spam-charsets: plain='UTF-8' X-Resolved-to: greg@kroah.com X-Delivered-to: greg@kroah.com X-Mail-from: arndbergmann@gmail.com ARC-Seal: i=1; a=rsa-sha256; cv=none; d=messagingengine.com; s=arctest; t=1516373563; b=dBVpTIqBMf6KPCf80Sf0Zr062V48sheWs+jkdo7lv8TGbl1 wyelbLv40CbI5O0sCf+RrXRuVAZ0TU4Td5QSfqR5MqScUyrCyMwOOrDBjbBySOOf LAnlmPJKiSE9fjvQ2LheClX3eGk8cJQSKzyXFJlczWRjTQ+Ru53NjR3y4c3ccZzL bE8qDkbCU8i7EwU5JdOH5eDOtSVefviO0GYCFeXBZzCi/ZfgcwEkOvmXTNYsI+/q Is2Bkq8i0lnPPAk6efKzQibD4qBFZjdtdQIA7OD+9ykMtw7yqHAeYYHEoSK/dVGl DAlp0gFpq0aPhY16p4GE2uAacIZKZ4RwKfxzcyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=mime-version:sender:in-reply-to :references:from:date:message-id:subject:to:cc:content-type; s= arctest; t=1516373563; bh=GrxljqtvOL2n2x/XwCiP7MVoL1JI5LFyW/zxAA /B9sE=; b=elOOvNXbGfCMLjXsraIubefKMvhcDaY3EVOtdbzDBeXsgZIj5k+ngY i4UtSexJkDh/eT+LhL145wIf/NoxKV5v7pJrgRGr7ekCe1Z4GPa+3Prhqu3NUst3 wDmoCs5blOCFO+zaUyfskV/Y88GV2CjFWCzeSsj9zRhHQKXopQHoOwmctGpyujTz 6Xnw+miIjiBe7MIq1ih3QBkqzm1FuBoE+W7KzpkvvsA687JWgAJ095q9pvbEqbTQ vesbVRlOvIB3UeaYhVXZWR/AFvtreiGQw963eHVkQeJvalK5d5X4O1qeJRBNrHjU a3NJ36Eyl+AsGIbmT6iDZNE2UpiJn/Sg== ARC-Authentication-Results: i=1; mx5.messagingengine.com; arc=none (no signatures found); dkim=pass (2048-bit rsa key sha256) header.d=gmail.com header.i=@gmail.com header.b=LIOqeZL0 x-bits=2048 x-keytype=rsa x-algorithm=sha256 x-selector=20161025; dmarc=none (p=none,d=none) header.from=arndb.de; iprev=pass policy.iprev=209.85.218.66 (mail-oi0-f66.google.com); spf=pass smtp.mailfrom=arndbergmann@gmail.com smtp.helo=mail-oi0-f66.google.com; x-aligned-from=fail; x-google-dkim=pass (2048-bit rsa key) header.d=1e100.net header.i=@1e100.net header.b=i4twI+Fa; x-ptr=pass x-ptr-helo=mail-oi0-f66.google.com x-ptr-lookup=mail-oi0-f66.google.com; x-return-mx=pass smtp.domain=gmail.com smtp.result=pass smtp_is_org_domain=yes header.domain=arndb.de header.result=pass header_is_org_domain=yes; x-tls=pass version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128 Authentication-Results: mx5.messagingengine.com; arc=none (no signatures found); dkim=pass (2048-bit rsa key sha256) header.d=gmail.com header.i=@gmail.com header.b=LIOqeZL0 x-bits=2048 x-keytype=rsa x-algorithm=sha256 x-selector=20161025; dmarc=none (p=none,d=none) header.from=arndb.de; iprev=pass policy.iprev=209.85.218.66 (mail-oi0-f66.google.com); spf=pass smtp.mailfrom=arndbergmann@gmail.com smtp.helo=mail-oi0-f66.google.com; x-aligned-from=fail; x-google-dkim=pass (2048-bit rsa key) header.d=1e100.net header.i=@1e100.net header.b=i4twI+Fa; x-ptr=pass x-ptr-helo=mail-oi0-f66.google.com x-ptr-lookup=mail-oi0-f66.google.com; x-return-mx=pass smtp.domain=gmail.com smtp.result=pass smtp_is_org_domain=yes header.domain=arndb.de header.result=pass header_is_org_domain=yes; x-tls=pass version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128 X-Google-Smtp-Source: ACJfBovcqmAOz8JkjFPNNaq+srk+SRdTfhMZu4oQsrnNEG2tX7h9z1Qhuj1JWXvbC5eZOGcBbb8v9FiywdGLtS/VHs0= MIME-Version: 1.0 Sender: arndbergmann@gmail.com In-Reply-To: References: From: Arnd Bergmann Date: Fri, 19 Jan 2018 15:52:40 +0100 X-Google-Sender-Auth: 4Hxl1mMxOI6spKTdqSSxDPLTBis Message-ID: Subject: Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings To: Greentime Hu Cc: Greentime , Linux Kernel Mailing List , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Networking , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , linux-serial@vger.kernel.org, Geert Uytterhoeven , Linus Walleij , Mark Rutland , Greg KH , Guo Ren , Randy Dunlap , David Miller , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Vincent Chen , Rick Chen , Zong Li Content-Type: text/plain; charset="UTF-8" X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Fri, Jan 19, 2018 at 3:32 PM, Greentime Hu wrote: > 2018-01-18 19:02 GMT+08:00 Arnd Bergmann : >> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu wrote: >>> From: Greentime Hu >>> >>> This patch adds nds32 CPU binding documents. >>> >>> Signed-off-by: Vincent Chen >>> Signed-off-by: Rick Chen >>> Signed-off-by: Zong Li >>> Signed-off-by: Greentime Hu >>> Reviewed-by: Rob Herring >>> --- >>> Documentation/devicetree/bindings/nds32/cpus.txt | 37 ++++++++++++++++++++++ >>> 1 file changed, 37 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt >>> >>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt >>> new file mode 100644 >>> index 0000000..9a52937 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt >>> @@ -0,0 +1,37 @@ >>> +* Andestech Processor Binding >>> + >>> +This binding specifies what properties must be available in the device tree >>> +representation of a Andestech Processor Core, which is the root node in the >>> +tree. >>> + >>> +Required properties: >>> + >>> + - compatible: >>> + Usage: required >>> + Value type: >>> + Definition: should be one of: >>> + "andestech,n13" >>> + "andestech,n15" >>> + "andestech,d15" >>> + "andestech,n10" >>> + "andestech,d10" >>> + "andestech,nds32v3" >> >> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that >> the device tree should always list 'andestech,nds32v3' as the most >> generic 'compatible' value and list exactly one of the others in >> addition. > I will remove the others and just left "andestech,nds32v3" in here. No, is not what we want here, the CPU node should list exactly which core is used, what we need in the description is a clarification that andestech,nds32v3 must be used in addition to the more specific string. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings Date: Fri, 19 Jan 2018 15:52:40 +0100 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Cc: Greentime , Linux Kernel Mailing List , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Networking , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Geert Uytterhoeven , Linus Walleij , Mark Rutland , Greg KH , Guo Ren Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: netdev.vger.kernel.org On Fri, Jan 19, 2018 at 3:32 PM, Greentime Hu wrote: > 2018-01-18 19:02 GMT+08:00 Arnd Bergmann : >> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu wrote: >>> From: Greentime Hu >>> >>> This patch adds nds32 CPU binding documents. >>> >>> Signed-off-by: Vincent Chen >>> Signed-off-by: Rick Chen >>> Signed-off-by: Zong Li >>> Signed-off-by: Greentime Hu >>> Reviewed-by: Rob Herring >>> --- >>> Documentation/devicetree/bindings/nds32/cpus.txt | 37 ++++++++++++++++++++++ >>> 1 file changed, 37 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt >>> >>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt >>> new file mode 100644 >>> index 0000000..9a52937 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt >>> @@ -0,0 +1,37 @@ >>> +* Andestech Processor Binding >>> + >>> +This binding specifies what properties must be available in the device tree >>> +representation of a Andestech Processor Core, which is the root node in the >>> +tree. >>> + >>> +Required properties: >>> + >>> + - compatible: >>> + Usage: required >>> + Value type: >>> + Definition: should be one of: >>> + "andestech,n13" >>> + "andestech,n15" >>> + "andestech,d15" >>> + "andestech,n10" >>> + "andestech,d10" >>> + "andestech,nds32v3" >> >> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that >> the device tree should always list 'andestech,nds32v3' as the most >> generic 'compatible' value and list exactly one of the others in >> addition. > I will remove the others and just left "andestech,nds32v3" in here. No, is not what we want here, the CPU node should list exactly which core is used, what we need in the description is a clarification that andestech,nds32v3 must be used in addition to the more specific string. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings Date: Fri, 19 Jan 2018 15:52:40 +0100 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Greentime Hu Cc: Greentime , Linux Kernel Mailing List , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Networking , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Geert Uytterhoeven , Linus Walleij , Mark Rutland , Greg KH , Guo Ren List-Id: devicetree@vger.kernel.org On Fri, Jan 19, 2018 at 3:32 PM, Greentime Hu wrote: > 2018-01-18 19:02 GMT+08:00 Arnd Bergmann : >> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu wrote: >>> From: Greentime Hu >>> >>> This patch adds nds32 CPU binding documents. >>> >>> Signed-off-by: Vincent Chen >>> Signed-off-by: Rick Chen >>> Signed-off-by: Zong Li >>> Signed-off-by: Greentime Hu >>> Reviewed-by: Rob Herring >>> --- >>> Documentation/devicetree/bindings/nds32/cpus.txt | 37 ++++++++++++++++++++++ >>> 1 file changed, 37 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt >>> >>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt >>> new file mode 100644 >>> index 0000000..9a52937 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt >>> @@ -0,0 +1,37 @@ >>> +* Andestech Processor Binding >>> + >>> +This binding specifies what properties must be available in the device tree >>> +representation of a Andestech Processor Core, which is the root node in the >>> +tree. >>> + >>> +Required properties: >>> + >>> + - compatible: >>> + Usage: required >>> + Value type: >>> + Definition: should be one of: >>> + "andestech,n13" >>> + "andestech,n15" >>> + "andestech,d15" >>> + "andestech,n10" >>> + "andestech,d10" >>> + "andestech,nds32v3" >> >> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that >> the device tree should always list 'andestech,nds32v3' as the most >> generic 'compatible' value and list exactly one of the others in >> addition. > I will remove the others and just left "andestech,nds32v3" in here. No, is not what we want here, the CPU node should list exactly which core is used, what we need in the description is a clarification that andestech,nds32v3 must be used in addition to the more specific string. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html