From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9E92C433EF for ; Tue, 7 Sep 2021 15:22:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F6C961102 for ; Tue, 7 Sep 2021 15:22:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345108AbhIGPXo (ORCPT ); Tue, 7 Sep 2021 11:23:44 -0400 Received: from mout.kundenserver.de ([217.72.192.75]:45949 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345019AbhIGPXn (ORCPT ); Tue, 7 Sep 2021 11:23:43 -0400 Received: from mail-wr1-f46.google.com ([209.85.221.46]) by mrelayeu.kundenserver.de (mreue108 [213.165.67.113]) with ESMTPSA (Nemesis) id 1N5mSj-1n2aSF0CeR-017An7; Tue, 07 Sep 2021 17:22:36 +0200 Received: by mail-wr1-f46.google.com with SMTP id t18so4286991wrb.0; Tue, 07 Sep 2021 08:22:35 -0700 (PDT) X-Gm-Message-State: AOAM531Qj5eAw082QSGq2LSDC9NOTCV/5nBOC8L2hA7BCC+/VXXbLwoT gV1hOIvFb2DS2s0HJpRMedZfa6Pph+Nt8m35YC0= X-Google-Smtp-Source: ABdhPJy58uScJqBW+UrC1EYruygZaDSlaishAvDFwCVWkwTrM6LrtBlVbOuI4LZO9PhoP1L02EP4ZshmBSt6whgyAaA= X-Received: by 2002:adf:c10b:: with SMTP id r11mr19521551wre.336.1631028155500; Tue, 07 Sep 2021 08:22:35 -0700 (PDT) MIME-Version: 1.0 References: <20210907102722.47543-1-bert@biot.com> <20210907102722.47543-5-bert@biot.com> In-Reply-To: From: Arnd Bergmann Date: Tue, 7 Sep 2021 17:22:19 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 4/5] ARM: Add basic support for Airoha EN7523 SoC To: Daniel Palmer Cc: Arnd Bergmann , Bert Vermeulen , Russell King , Linus Walleij , Andrew Morton , Geert Uytterhoeven , Anshuman Khandual , Marc Zyngier , Mark Rutland , John Crispin , Ard Biesheuvel , YiFei Zhu , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Mike Rapoport , linux-arm-kernel , Linux Kernel Mailing List , DTML Content-Type: text/plain; charset="UTF-8" X-Provags-ID: V03:K1:rQn/ggVZMxa0impJfQu8ANKJ9Dp7zg0dW2eal7JvpWIuEul96Ar Xkr3e0hnz1cLDzZGn+sApKVyW1IMpPGEzJq6V5YWxQHyIkkCUtdRSW91FAK//0nFNd1sauu 0cZlJFVgQ9DrCUqAj/EIFb09cqN2HOAbM1p04UFUBphWUYZ/QX7MlI7qn1NG1py4UUqNU+L Ap67sOktLDWI2IZCcclIw== X-UI-Out-Filterresults: notjunk:1;V03:K0:pyPB3Zm4iTE=:2bqXNR9fPUqGjkg6buYqX4 VhRN3wA7ve8Fed0iN6H2fdosLHYx2IvCcwFbk1TwB4NigdPVZO9czH1gUfcF2ztr795zOOj8s tD9i4ofsEbIiKYTPdQojrf2Z79BLqf4splyTBekMSwJaqZCIUUx5FXpypoGiY3SxaniNW4FY1 11LicF6Ke8O26wmCxWmc8q5zEE2LMinz2q9PWjHW+LnsSvtB5os+JiTwxz+odx9J2G2lpH2zl gzBWR7UxnCgzBkQQdtTkKTpnAz622rXkBIRit5r3bc6Zvyke8kLPMl3drjlL6VJzjNVyuXq5C cRR9MgFnUK7Nzs6dooS5nOvFqTfGfQg9e/vp9Xy1iT2a3Y1ZhW05AaXOzoGUOD+K6j3BgJV/4 Et7Bymb2rt5LlmVnzpNtDNWY9U4bqVNdn+GLC9EHj7j6hZ4VetT/zKAV6r+zDHruIkrj9Y01+ +loiYxtD8wZZTZjNQmjbsi8EFRnuMibGI4dLeD8ZGl2qLdpf/kz3xrU4LRvw66Svn/smQoFUo QICUuDDiFvlj/npZNit+J8I3B1Xm/R+Jwr7nxiH2S7TjPWryN3WBRwUB1u5FZyOmt1tKFJ/nS vSgzbIN6KDPRwCc+0rgqCsWR0DMnsg6qpJTeYISdpvXXSEKiD3i4ILLpAPiAsfgCKqVXCeY14 uBW9Ca6FL3FVIFISQ72wpyQJoLBnxFYGfUMyEvEsjHK2ZrzY8zZXMlhQzmdbdpsfNJNXd6a/3 JpcK21ITUoeFyw7L6ZuuJUBnCZvi/j6dz7KYZQ== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 7, 2021 at 4:32 PM Daniel Palmer wrote: > On Tue, 7 Sept 2021 at 23:12, Arnd Bergmann wrote: > > > > I think the broken memory controller is still there so somehow I'd > > > need to get the heavy barrier to work in arm64. I haven't yet worked > > > out if that's even possible. > >I think I missed that part of the discussion, or I forgot about it already. > >What is the issue you are referring to here? > > Sorry. I should have put a bit more context. This is for the SSD268G > not the original target of this series. But a similar situation. > The SSD268G (according to the decompiled device tree) is the same > hardware as the MSTAR_V7 chips but with a Cortex A53 instead of the > Cortex A7. > So it probably has the same memory controller as the MSTAR_V7 stuff > and that memory controller is not coherent so it needs the kernel to > make sure memory requests are flushed out to memory before DMA > happens[0]. For arm I fixed that with the heavy mb callback. With > arm64 I have no idea how to fix that. Ok, got it. I do remember the Mstar SoCs having this problem. My feeling is that this should be possible to implement on arm64 as well using an erratum fixup with a configuration option, and possibly dynamic patching to avoid the worst effects when the workaround is built into the kernel but not needed. Whether this is acceptable or not is up to the arm64 architecture maintainers of course. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B886C433F5 for ; Tue, 7 Sep 2021 15:24:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B80D61102 for ; Tue, 7 Sep 2021 15:24:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3B80D61102 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arndb.de Authentication-Results: mail.kernel.org; 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Tue, 07 Sep 2021 15:22:45 +0000 Received: from mout.kundenserver.de ([212.227.126.134]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNcvo-0042Vq-Do for linux-arm-kernel@lists.infradead.org; Tue, 07 Sep 2021 15:22:42 +0000 Received: from mail-wr1-f51.google.com ([209.85.221.51]) by mrelayeu.kundenserver.de (mreue010 [213.165.67.97]) with ESMTPSA (Nemesis) id 1MryGj-1miAQK1YDF-00nwMi for ; Tue, 07 Sep 2021 17:22:37 +0200 Received: by mail-wr1-f51.google.com with SMTP id g16so3018731wrb.3 for ; Tue, 07 Sep 2021 08:22:35 -0700 (PDT) X-Gm-Message-State: AOAM533oJZbaNR2rNHxFMBq9iND3CWX6ruSbk9oITHoQaG+eCymOKYXA aUH0xFGazfgTeZWHCF8II4z1QExLecobNI2719o= X-Google-Smtp-Source: ABdhPJy58uScJqBW+UrC1EYruygZaDSlaishAvDFwCVWkwTrM6LrtBlVbOuI4LZO9PhoP1L02EP4ZshmBSt6whgyAaA= X-Received: by 2002:adf:c10b:: with SMTP id r11mr19521551wre.336.1631028155500; Tue, 07 Sep 2021 08:22:35 -0700 (PDT) MIME-Version: 1.0 References: <20210907102722.47543-1-bert@biot.com> <20210907102722.47543-5-bert@biot.com> In-Reply-To: From: Arnd Bergmann Date: Tue, 7 Sep 2021 17:22:19 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 4/5] ARM: Add basic support for Airoha EN7523 SoC To: Daniel Palmer Cc: Arnd Bergmann , Bert Vermeulen , Russell King , Linus Walleij , Andrew Morton , Geert Uytterhoeven , Anshuman Khandual , Marc Zyngier , Mark Rutland , John Crispin , Ard Biesheuvel , YiFei Zhu , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Mike Rapoport , linux-arm-kernel , Linux Kernel Mailing List , DTML X-Provags-ID: V03:K1:UfspkB32+TAs/a8XDLNTscxn27QVGpSPqsAQEy6NITlFq+usVxH djqPJPszu7m4Ea2BJfLvrzZh4ouQQ1Uh0zUaI+YT4LI1xoHMkcLe+1VvfwZsRgcAUuIpjiN JBq6zW953xvemXkjbG1dYXrSwVfZDVnqj8pJQc5SkH81bnvDd6M9aSjOcY6XnnEU3FGH3If LyOuLbfPmTJ/6ep8bJHOQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:Tw8Em80h+nc=:bvSP0be0qn95/tzmDy1aqv vQ3Ed9L1ibW4/yGPWWP3fQV5ddR15RRy1W1BFS7STwsRhdF+FE6iHNXZrZbQU5sPdSGf1RoQK Jn736SygKS1t1W3/HBJ7SG/PFPvF31BU4SGCq58x80BIUP8s0JnaTFVKQ0xbqlPpxWsbhXT1U B1tW1BhuHhh6KQiD+uO3ZFSOSgAmZRVUZzSSNE0Q+LEy2pXUpJ4jTd6cJKlOD8TyF+gU2hgvf 2E1qD+9MBC2jT5zVmqm4FyC1YCtos2bo5v+WsOfQlp+4TQJa4BrhLr0qIPZsobuIYJ07kCvUR WyjG6kle5eWnKMQrpJSevInAt+i9kiEh0S8ZYeeZy/76Xo6wfQ0RrkHnZlksZ010zwBlEkGlA PHo3sBpTmMtChjMwwLjqoaem2u07+xssMCVwxLaJRdmsdcTm507w2Nl8J1ipghNSc7WV5edj+ HVLtrlD+X2iG/e7pw5TpGUnGkticB2A6SpS+sAyq2EM71Fz9GzoC8Mg2W+ho8goYUiEW92rqd wbOKXOGAnmmSYXkeF3eSTy3ba/W4G1oQSVYNiFxhEj7m6M0xwGS/dVieYA0JIkUVVdcfMGU/N rhp8ZRw/8kjuK0v9FgAg2FufsF5NbaLznhFwCyKx1BTHeLGwRSgPb/sMniRmzPzRJikgAUfke jCHIhgw9CBV3eVmN1ctxikN7tFfAwKCKVQZ+3Iumsfxb2p698UUJgwnGKrJXEJwwnD1FCPc7S T+BIaTjnxn6ndkXt2dDkdIP8YdWmTKekvaGj5VAEe5Mr0DsbiSwEyTXY20piTmmK109whi/nO ny60/Jhs27+P2y3cWZobfgtQtr0Hr3moAcpcdKVpcYta5975fUfR+xHkOteskS3YTGfxN3B4G 8FSr7fiotQwcOQTGpgsg== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210907_082240_809082_F7629A20 X-CRM114-Status: GOOD ( 30.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 7, 2021 at 4:32 PM Daniel Palmer wrote: > On Tue, 7 Sept 2021 at 23:12, Arnd Bergmann wrote: > > > > I think the broken memory controller is still there so somehow I'd > > > need to get the heavy barrier to work in arm64. I haven't yet worked > > > out if that's even possible. > >I think I missed that part of the discussion, or I forgot about it already. > >What is the issue you are referring to here? > > Sorry. I should have put a bit more context. This is for the SSD268G > not the original target of this series. But a similar situation. > The SSD268G (according to the decompiled device tree) is the same > hardware as the MSTAR_V7 chips but with a Cortex A53 instead of the > Cortex A7. > So it probably has the same memory controller as the MSTAR_V7 stuff > and that memory controller is not coherent so it needs the kernel to > make sure memory requests are flushed out to memory before DMA > happens[0]. For arm I fixed that with the heavy mb callback. With > arm64 I have no idea how to fix that. Ok, got it. I do remember the Mstar SoCs having this problem. My feeling is that this should be possible to implement on arm64 as well using an erratum fixup with a configuration option, and possibly dynamic patching to avoid the worst effects when the workaround is built into the kernel but not needed. Whether this is acceptable or not is up to the arm64 architecture maintainers of course. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel