From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37196C433E0 for ; Wed, 10 Mar 2021 03:54:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E6E3B64FCD for ; Wed, 10 Mar 2021 03:54:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231144AbhCJDx2 (ORCPT ); Tue, 9 Mar 2021 22:53:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231519AbhCJDxH (ORCPT ); Tue, 9 Mar 2021 22:53:07 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB86CC061761 for ; Tue, 9 Mar 2021 19:53:06 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id p1so25368330edy.2 for ; Tue, 09 Mar 2021 19:53:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=V85TNfWqFZ1YWa4+0GmlbK4ntqljyBS3Rdg24ykQOq8=; b=T8WNl3ye+lgMOr3Hf7sVPy7jQOGqPpwD9/Jt8gsoFhzRrcvWM62VXcGTl47x2GnQkF CFwacwingV3+q1IbKsKuyuNfcEGRf0Ty3T14iZATP6JfeNfPlVlYa7CuuimjxHHfsSIi opLIGbAKyuXFTAmfxA41bk3cXk/xy1w2rk4+3SqRFMx/Ngj003h4ewfssX3ZHmw9lnde Znk/TrU4AuthDorMF34LO58IV18yCB+OuLOEd+WQgbnmZrUZp6MiyLTf8dL1D67Vl69g eW24XhNgo9w39ZjUqGYpyVmfu3C1r7XCYS213qniCd7nzkoGWu9CUs1l77guT1o83qOA z1NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=V85TNfWqFZ1YWa4+0GmlbK4ntqljyBS3Rdg24ykQOq8=; b=UeXd5ZevGyAZFCMAFwWT8J+CG1SAezpAZkaTySQZE3Zkzomj9/YRTZwyB0mBQGMzuI jUsik3ZTotxbIjGhcLbuzqNy8OlPGBTC1UKh/C20C9YXsN5aEYYlBxXiQfP/kLsw6mU6 +C0zWDwB2k1EyN9fMlF08SHdWYddG9v1RXsVwvP+z3mlOY4qJIyM85mF1eH6LBlCoEFO qKpdX7Png2GDcSwzKVjr3sS5g3CYpTISrQkqXV7cbbeTIzxu8o2PWaVjnougiBA2c4yj ljFDZH7w5+skvj8G+E/LpGMYiH0vNxedq5PydVxr6cXuJs54FaJc74WQetsslXMB++9c bQlQ== X-Gm-Message-State: AOAM530B0JaniQvc/RP1iTkO5kYY3cxVYtOaPQzGdeB02Zlnvtrna0LG e7nyowoVB27RuAv/wGQPT7+DDGEYh6y1XEXAaCf+4g== X-Google-Smtp-Source: ABdhPJzB8cRnMmkiPZTcmJvX4c2OtzugP+mbvj2rl8DsysINHwrol+RNZBcMO6TXO06YDz3jiaOXzCAzsTSfru8WhXM= X-Received: by 2002:aa7:c496:: with SMTP id m22mr935303edq.292.1615348385484; Tue, 09 Mar 2021 19:53:05 -0800 (PST) MIME-Version: 1.0 References: <20210304034141.7062-1-brad@pensando.io> <20210304034141.7062-4-brad@pensando.io> In-Reply-To: From: Brad Larson Date: Tue, 9 Mar 2021 19:52:54 -0800 Message-ID: Subject: Re: [PATCH 3/8] spi: dw: Add support for Pensando Elba SoC SPI To: Linus Walleij Cc: Linux ARM , Arnd Bergmann , Bartosz Golaszewski , Mark Brown , Serge Semin , Adrian Hunter , Ulf Hansson , Olof Johansson , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Thu, Mar 4, 2021 at 12:48 AM Linus Walleij wrote: > On Thu, Mar 4, 2021 at 4:42 AM Brad Larson wrote: > > > The Pensando Elba SoC uses a GPIO based chip select > > for two DW SPI busses with each bus having two > > chip selects. > > > > Signed-off-by: Brad Larson > > I agree with Serge's comments here: the existing cs callback should > work for your SoC, you should only need the new compatible string. > > I see why you need the special GPIO driver for this now, as that > is obviously driven by totally different hardware. > > Yours, > Linus Walleij Thanks Serge and Linus for the review. In the SPI driver, the reason we need our own set_cs function is that our DW SPI controller only supports intrinsic 2 chip-select pins. This is the standard DW set_cs function: void dw_spi_set_cs(struct spi_device *spi, bool enable) { struct dw_spi *dws = spi_controller_get_devdata(spi->controller); bool cs_high = !!(spi->mode & SPI_CS_HIGH); /* * DW SPI controller demands any native CS being set in order to * proceed with data transfer. So in order to activate the SPI * communications we must set a corresponding bit in the Slave * Enable register no matter whether the SPI core is configured to * support active-high or active-low CS level. */ if (cs_high == enable) dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); else dw_writel(dws, DW_SPI_SER, 0); } The dw_writel function argument DW_SPI_SER, BIT(spi->chip_select) works for chip-select 0 & 1, but not for 2 & 3, as the IP only implements bits [1:0] in the DW_SPI_SER register. In the Elba SoC we require GPIO-style chip-selects, our own set_cs function, and we always use bit 0 of DW_SPI_SER to start the serial machine, not as a chip-select control. In the dw_spi_set_cs() function the below else clause is never taken and leads to confusion. } else { /* * Using the intrinsic DW chip-select; set the * appropriate CS. */ dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); } This else clause will be removed in patch set V2. I tried the generic dw_spi_set_cs() thinking it would just start the serial machine while the Elba spics drives the gpio chip select, that didn't work. I will take another look at it as I work on V2 of the patchset to see exactly what breaks during spi init. Best, Brad From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41967C433DB for ; Wed, 10 Mar 2021 03:55:49 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D578A64F80 for ; Wed, 10 Mar 2021 03:55:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D578A64F80 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pensando.io Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From:In-Reply-To: References:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aIvb/oFbdK0xAOrKib/eXQNhm84jkFkubB37fX2Hi5c=; b=Z/XHYCp0c86bkvw95o2Gum9Tk afs9HtNlC///XgM8LjaSSKCSSpuSIqT+Sy25YPkVuSaZ/oxR4o4n9hdGJ5I0zTtcdjPM0H+a41m9x yBeHDb4LsER7GYSBv2K/dlUp3t+fCY2cTJs4FX3Q6/Pk8XHo4gR29lEX9KBUUytWCyYPjzpZbpWXB 6Sk2mnucCjhmsKObDmhuisqMffkUNdZU5BxpvTsxKOioGno7UUuU2NyIrmojR3tWTDRBPQn4OqH7A GgOeXJAAquCKkdXs2vO375HNAciGZMVQJyfVPTH8SF34eLw+PsP6y1/85b3kzDFz9fzHsJP6X7co7 BYI0Rli+g==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lJpv8-005xiC-BF; Wed, 10 Mar 2021 03:54:02 +0000 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lJpuG-005xer-1M for linux-arm-kernel@lists.infradead.org; Wed, 10 Mar 2021 03:53:21 +0000 Received: by mail-ed1-x52a.google.com with SMTP id w9so25243672edt.13 for ; Tue, 09 Mar 2021 19:53:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=V85TNfWqFZ1YWa4+0GmlbK4ntqljyBS3Rdg24ykQOq8=; b=T8WNl3ye+lgMOr3Hf7sVPy7jQOGqPpwD9/Jt8gsoFhzRrcvWM62VXcGTl47x2GnQkF CFwacwingV3+q1IbKsKuyuNfcEGRf0Ty3T14iZATP6JfeNfPlVlYa7CuuimjxHHfsSIi opLIGbAKyuXFTAmfxA41bk3cXk/xy1w2rk4+3SqRFMx/Ngj003h4ewfssX3ZHmw9lnde Znk/TrU4AuthDorMF34LO58IV18yCB+OuLOEd+WQgbnmZrUZp6MiyLTf8dL1D67Vl69g eW24XhNgo9w39ZjUqGYpyVmfu3C1r7XCYS213qniCd7nzkoGWu9CUs1l77guT1o83qOA z1NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=V85TNfWqFZ1YWa4+0GmlbK4ntqljyBS3Rdg24ykQOq8=; b=VusOZbxiBh6nPgNn5zwmKXq5GVFM93hPE7dgr9tH57NRsIDEVW4W9GcPZ7MVpq7Vvs DB633hm6olx0F+oyXrxoR+3qeGf1Ckucc3vE7Wqu+tUvLW7SdnB9sJ0Hg4afQSSN/nD0 5yJaS/xz9NR7cC4DQ6eTqphrcMKplV/ZS9NUmSDcNuP4Kd1PJCp8Gv1iBtb99vgMHJRs 7i+JxsQXz5xVzjp35e8mEps+9Tsg7PiAySudRZvm8DEltkaKpDp8aWDsvf4S7/l3KsZI /U8LrwZjA28L6351WAA6P5bOj81Eca7dt4SQdYOu9Fa0SHSdvu5PtSn7V7k/TbfBVDCD t6bQ== X-Gm-Message-State: AOAM533lq2H+AHi6C2ljRUG4x5+J4BYeml33fNdAF+fsbyEVw3Tbo/hg 5Q5AMdxlRsgOr0CkbpVgIenRPI5kfNLN/RHtQr385Q== X-Google-Smtp-Source: ABdhPJzB8cRnMmkiPZTcmJvX4c2OtzugP+mbvj2rl8DsysINHwrol+RNZBcMO6TXO06YDz3jiaOXzCAzsTSfru8WhXM= X-Received: by 2002:aa7:c496:: with SMTP id m22mr935303edq.292.1615348385484; Tue, 09 Mar 2021 19:53:05 -0800 (PST) MIME-Version: 1.0 References: <20210304034141.7062-1-brad@pensando.io> <20210304034141.7062-4-brad@pensando.io> In-Reply-To: From: Brad Larson Date: Tue, 9 Mar 2021 19:52:54 -0800 Message-ID: Subject: Re: [PATCH 3/8] spi: dw: Add support for Pensando Elba SoC SPI To: Linus Walleij Cc: Linux ARM , Arnd Bergmann , Bartosz Golaszewski , Mark Brown , Serge Semin , Adrian Hunter , Ulf Hansson , Olof Johansson , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_035317_996090_40FFC539 X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 4, 2021 at 12:48 AM Linus Walleij wrote: > On Thu, Mar 4, 2021 at 4:42 AM Brad Larson wrote: > > > The Pensando Elba SoC uses a GPIO based chip select > > for two DW SPI busses with each bus having two > > chip selects. > > > > Signed-off-by: Brad Larson > > I agree with Serge's comments here: the existing cs callback should > work for your SoC, you should only need the new compatible string. > > I see why you need the special GPIO driver for this now, as that > is obviously driven by totally different hardware. > > Yours, > Linus Walleij Thanks Serge and Linus for the review. In the SPI driver, the reason we need our own set_cs function is that our DW SPI controller only supports intrinsic 2 chip-select pins. This is the standard DW set_cs function: void dw_spi_set_cs(struct spi_device *spi, bool enable) { struct dw_spi *dws = spi_controller_get_devdata(spi->controller); bool cs_high = !!(spi->mode & SPI_CS_HIGH); /* * DW SPI controller demands any native CS being set in order to * proceed with data transfer. So in order to activate the SPI * communications we must set a corresponding bit in the Slave * Enable register no matter whether the SPI core is configured to * support active-high or active-low CS level. */ if (cs_high == enable) dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); else dw_writel(dws, DW_SPI_SER, 0); } The dw_writel function argument DW_SPI_SER, BIT(spi->chip_select) works for chip-select 0 & 1, but not for 2 & 3, as the IP only implements bits [1:0] in the DW_SPI_SER register. In the Elba SoC we require GPIO-style chip-selects, our own set_cs function, and we always use bit 0 of DW_SPI_SER to start the serial machine, not as a chip-select control. In the dw_spi_set_cs() function the below else clause is never taken and leads to confusion. } else { /* * Using the intrinsic DW chip-select; set the * appropriate CS. */ dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); } This else clause will be removed in patch set V2. I tried the generic dw_spi_set_cs() thinking it would just start the serial machine while the Elba spics drives the gpio chip select, that didn't work. I will take another look at it as I work on V2 of the patchset to see exactly what breaks during spi init. Best, Brad _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel