From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EDC2C4727E for ; Wed, 7 Oct 2020 07:48:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1D6620870 for ; Wed, 7 Oct 2020 07:48:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Zkp2OT1d" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727786AbgJGHsb (ORCPT ); Wed, 7 Oct 2020 03:48:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726041AbgJGHsa (ORCPT ); Wed, 7 Oct 2020 03:48:30 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B1D4C061755; Wed, 7 Oct 2020 00:48:30 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id l17so1109349edq.12; Wed, 07 Oct 2020 00:48:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aIxS3a1/Usr8Ax4oAxdfAOqWyGV3Kir87fjE4KL3SWA=; b=Zkp2OT1dBxSRUm4UBunol1MkXZDcFD/RX1FhRudN2vPdQItuQfLLBD3IMuvchLOMGo 2l3/52w502E1A9Vumv8M3LN2i/KKNZKr9OFE/7GUmTIW3iU7/MCyGd2/1x9X/BhT4QqT bhkaqv5wjJIYoxKxZt1b9KCCcbf+Q0s0hIlWSClE3lzP2+pDq15tkVXZv4agKtxnA2b+ F4q6R2X7yWm+3XPDnoKFp1lMjcoOwdYbLiFvkFzrga9MwWiOjjcRTCd8+nYbDLu1IGia yIPZbwRBcdrcONxBt9ekMT0Q7X3NJnFTCo77i8W6IQ/Bg9l/85Di3yFpNJZbmrT8XGCn sgZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aIxS3a1/Usr8Ax4oAxdfAOqWyGV3Kir87fjE4KL3SWA=; b=Ljo3/a/+jyhGOok6Lj6PRkctxPCJUVR97Gl84H1SZDOywveAPFhAgRJtmF1ExX3MLR AAPS4IqwfkcSyWqYkmJteNmZethl1VBI2T0CVx1XOIeOu6zHZSJCfAywIX3wP31XMQE7 9m+/y77QFp8lnAGOEKrv+9XAxO2XBkFzNfpkoYpr3U3x6Qni0Mvo3wwyO4D51YJxN3Pe vYIgqBFg4YYRv22xsa6oRtDVWahmmGKuYh0sh58fZmods5WWsnzMo03j7/T/ILgx89sA Axwr42mwXD9TBS5VVlc1WQ6KTrmQ/6Iop6cvZGuiaWw7KVok2ZUwmSNGH7a5kGxF4scz 91kg== X-Gm-Message-State: AOAM531YZ58Rws49P2aCNOtr78O/Fz7T5FBLMlBEtaehJxWLILgJj+D6 j9MeU/wSMv3DV7AaeK/iD3wOqEWBZxn6Iu7FQmA= X-Google-Smtp-Source: ABdhPJwsp4gWugt5zYoY/WqXwmjYqS76upRymp0LRLz2XkAXOwb1wEAWa9UTuA6na/2PbKPQ0dVTqSmOh4Y6FDI5ZkY= X-Received: by 2002:a50:b063:: with SMTP id i90mr2229989edd.187.1602056909027; Wed, 07 Oct 2020 00:48:29 -0700 (PDT) MIME-Version: 1.0 References: <20201003075514.32935-1-haifeng.zhao@intel.com> <20201003075514.32935-4-haifeng.zhao@intel.com> <20201004191329.GA27962@wunner.de> In-Reply-To: <20201004191329.GA27962@wunner.de> From: Ethan Zhao Date: Wed, 7 Oct 2020 15:48:17 +0800 Message-ID: Subject: Re: [PATCH v7 3/5] PCI: pciehp: check and wait port status out of DPC before handling DLLSC and PDC To: Lukas Wunner Cc: Ethan Zhao , Bjorn Helgaas , Oliver , ruscur@russell.cc, Andy Shevchenko , Stuart Hayes , Alexandru Gagniuc , Mika Westerberg , linux-pci , Linux Kernel Mailing List , "Raj, Ashok" , Sathyanarayanan Kuppuswamy Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Lukas, On Mon, Oct 5, 2020 at 3:13 AM Lukas Wunner wrote: > > On Sat, Oct 03, 2020 at 03:55:12AM -0400, Ethan Zhao wrote: > > When root port has DPC capability and it is enabled, then triggered by > > errors, DPC DLLSC and PDC etc interrupts will be sent to DPC driver, pciehp > > drivers almost at the same time. > > Do the DLLSC and PDC events occur as a result of handling the error > or do they occur independently? They could happen independently if links were recovered then the card was removed. They could happen as a result of handling the errors the same time. So don't assume DLLSC and PDC all occur at the same time. > > If the latter, I don't see how we can tell whether the card in the > slot is still the same. If PDC happens, the card in the slot might not be the same. so hot-removal /hot -plugin handling follows the PDC event. > > If the former, holding the hotplug slot's reset_lock and doing something > along the lines of pciehp_reset_slot() (or calling it directly) might > solve the race. DPC reset is done by hardware, only AER calls pciehp_reset_slot() as recovery handling initiated by software. Thanks, Ethan > > Thanks, > > Lukas