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bh=VEdXx/unhoAspyNdeypuQARVF7GT/IGCOOxAclfE3Po=; b=KVn3P7AVB6cpQGS9pOwCFvYETEmbOEDdRmJ83EUY57lLl1E+h3gZQUhqqO/D3B/16H OSSQU7DNfhf7UQGW937lzE0arrdy5938mmMZegTXvwg3G81toZLoEhmLbw1Pv8uX0sCa V8vi8RuI+SpUE3eZA7Y9JzwkG9iYBtM/gud3qnk2fnIgtZVQv7LMZBqrQC5TMjpiKiog gmj6tzlO+8d8lkOYxU0+gN3HMG2ULaKGzY4uaTHkGKUAsRHtHCN+1MGWbwyyHxARutvB mLLH1frKy0HJaWnYI6bcyV6uzboQsChdjaABAdhplygMTPU/TZtCm51xO9rXmmfOWISX GepQ== X-Gm-Message-State: APjAAAWI8t2oUldq5SZLQDLYBE0n6XT/aCi5hjeIDbqMVgxKxi2xsJan 1x8FmVZCyXYL7RT3SxMPy7g8IprR6pYKn8kH/saLTRSc X-Google-Smtp-Source: APXvYqznhgLkah+3wRJ+x7D/C6vgv26plF47/dWiTEoYReVvMDPnUxM+auZwl5KrDTECXewJPmnw9etfbD3TKtVLmg0= X-Received: by 2002:a9d:6b0a:: with SMTP id g10mr11180447otp.303.1570779973032; Fri, 11 Oct 2019 00:46:13 -0700 (PDT) MIME-Version: 1.0 References: <20191010092526.10419-1-narmstrong@baylibre.com> <20191010092526.10419-5-narmstrong@baylibre.com> <20191010132601.GA10110@arm.com> <44f1771f-d640-f23d-995f-7bfcadd213bc@baylibre.com> <20191010173152.GA575@arm.com> In-Reply-To: <20191010173152.GA575@arm.com> From: Daniel Vetter Date: Fri, 11 Oct 2019 09:46:01 +0200 Message-ID: Subject: Re: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane To: Ayan Halder X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191011_004615_704243_36464B06 X-CRM114-Status: GOOD ( 34.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , "khilman@baylibre.com" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" , nd , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 10, 2019 at 7:32 PM Ayan Halder wrote: > > On Thu, Oct 10, 2019 at 03:41:15PM +0200, Neil Armstrong wrote: > > Hi Ayan, > > > > On 10/10/2019 15:26, Ayan Halder wrote: > > > On Thu, Oct 10, 2019 at 11:25:23AM +0200, Neil Armstrong wrote: > > >> This adds all the OSD configuration plumbing to support the AFBC decoders > > >> path to display of the OSD1 plane. > > >> > > >> The Amlogic GXM and G12A AFBC decoders are integrated very differently. > > >> > > >> The Amlogic GXM has a direct output path to the OSD1 VIU pixel input, > > >> because the GXM AFBC decoder seem to be a custom IP developed by Amlogic. > > >> > > >> On the other side, the Amlogic G12A AFBC decoder seems to be an external > > >> IP that emit pixels on an AXI master hooked to a "Mali Unpack" block > > >> feeding the OSD1 VIU pixel input. > > >> This uses a weird "0x1000000" internal HW physical address on both > > >> sides to transfer the pixels. > > >> > > >> For Amlogic GXM, the supported pixel formats are the same as the normal > > >> linear OSD1 mode. > > >> > > >> On the other side, Amlogic added support for all AFBC v1.2 formats for > > >> the G12A AFBC integration. > > >> > > >> For simplicity, we stick to the already supported formats for now. > > >> > > >> Signed-off-by: Neil Armstrong > > >> --- > > >> drivers/gpu/drm/meson/meson_crtc.c | 2 + > > >> drivers/gpu/drm/meson/meson_drv.h | 4 + > > >> drivers/gpu/drm/meson/meson_plane.c | 215 ++++++++++++++++++++++++---- > > >> 3 files changed, 190 insertions(+), 31 deletions(-) > > >> > > >> diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c > > >> index 57ae1c13d1e6..d478fa232951 100644 > > >> --- a/drivers/gpu/drm/meson/meson_crtc.c > > >> +++ b/drivers/gpu/drm/meson/meson_crtc.c > > >> @@ -281,6 +281,8 @@ void meson_crtc_irq(struct meson_drm *priv) > > >> if (priv->viu.osd1_enabled && priv->viu.osd1_commit) { > > >> writel_relaxed(priv->viu.osd1_ctrl_stat, > > >> priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); > > >> + writel_relaxed(priv->viu.osd1_ctrl_stat2, > > >> + priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > > >> writel_relaxed(priv->viu.osd1_blk0_cfg[0], > > >> priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); > > >> writel_relaxed(priv->viu.osd1_blk0_cfg[1], > > >> diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h > > >> index 60f13c6f34e5..de25349be8aa 100644 > > >> --- a/drivers/gpu/drm/meson/meson_drv.h > > >> +++ b/drivers/gpu/drm/meson/meson_drv.h > > >> @@ -53,8 +53,12 @@ struct meson_drm { > > >> bool osd1_enabled; > > >> bool osd1_interlace; > > >> bool osd1_commit; > > >> + bool osd1_afbcd; > > >> uint32_t osd1_ctrl_stat; > > >> + uint32_t osd1_ctrl_stat2; > > >> uint32_t osd1_blk0_cfg[5]; > > >> + uint32_t osd1_blk1_cfg4; > > >> + uint32_t osd1_blk2_cfg4; > > >> uint32_t osd1_addr; > > >> uint32_t osd1_stride; > > >> uint32_t osd1_height; > > >> diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c > > >> index 5e798c276037..412941aa8402 100644 > > >> --- a/drivers/gpu/drm/meson/meson_plane.c > > >> +++ b/drivers/gpu/drm/meson/meson_plane.c > > >> @@ -23,6 +23,7 @@ > > >> #include "meson_plane.h" > > >> #include "meson_registers.h" > > >> #include "meson_viu.h" > > >> +#include "meson_osd_afbcd.h" > > >> > > >> /* OSD_SCI_WH_M1 */ > > >> #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w) > > >> @@ -92,12 +93,38 @@ static int meson_plane_atomic_check(struct drm_plane *plane, > > >> false, true); > > >> } > > >> > > >> +#define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \ > > >> + AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \ > > >> + AFBC_FORMAT_MOD_YTR | \ > > >> + AFBC_FORMAT_MOD_SPARSE | \ > > >> + AFBC_FORMAT_MOD_SPLIT) > > >> + > > >> /* Takes a fixed 16.16 number and converts it to integer. */ > > >> static inline int64_t fixed16_to_int(int64_t value) > > >> { > > >> return value >> 16; > > >> } > > >> > > >> +static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv) > > >> +{ > > >> + u32 line_stride = 0; > > >> + > > >> + switch (priv->afbcd.format) { > > >> + case DRM_FORMAT_RGB565: > > >> + line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7; > > >> + break; > > >> + case DRM_FORMAT_RGB888: > > >> + case DRM_FORMAT_XRGB8888: > > >> + case DRM_FORMAT_ARGB8888: > > >> + case DRM_FORMAT_XBGR8888: > > >> + case DRM_FORMAT_ABGR8888: > > > Please have a look at > > > https://www.kernel.org/doc/html/latest/gpu/afbc.html for our > > > recommendation. We suggest that *X* formats are avoided. > > > > > > Also, for interoperability and maximum compression efficiency (with > > > AFBC_FORMAT_MOD_YTR), we suggest the following order :- > > > > > > Component 0: R > > > Component 1: G > > > Component 2: B > > > Component 3: A (if available) > > > > > > Sorry I don't understand, you ask me to limit AFBC to ABGR8888 ? > > Apologies for the confusion, as per the link, the formats which are > suggested with AFBC_FORMAT_MOD_YTR are the BGR/ABGR formats (as > listed in the 'AFBC formats' table) > > Thus, any other permutation of the components might make it incompatible > with some other AFBC producers/consumers. Uh, that's not how this is supposed to be used. Drivers are meant to expose _everything_ they support (bonus if you roughly sort it in preference order). Userspace then computes the intersection of modifiers/formats supported by all devices it needs to share a buffer with. Allowing that was the entire point of modifiers, if we artificially limit to the common denominator we're back "only linear works everywhere". -Daniel > > > > > But why if the HW (GPU and DPU) is capable of ? > > > > Isn't it an userspace choice ? I understand XRGB8888 is a waste > > of memory space and compression efficiency, but this is not the > > kernel driver's to decide this, right ? > It is a reccomendation by the AFBC spec. As far as I understand, it > depends upon the implementor of the AFBC spec(ie dpu, gpu, vpu, etc) > to allow/disallow *X* formats for AFBC encoding/decoding. > > > > > For interoperability I'll understand recommending a minimal set > > of modifiers and formats. But here, each platform is also limited > > by it's GPU capabilites aswell. > Agreed > > > > > Limiting to ABGR8888 would discard like every non-Android renderers, > > using AFBC, I'm not sure it's the kernels driver's responsibility. > I am not familiar with non-Android renderers. > > > > > > > > Thus, DRM_FORMAT_ABGR, DRM_FORMAT_BGR should only be allowed. > > >> + line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7; > > >> + break; > > >> + } > > >> + > > >> + return ((line_stride + 1) >> 1) << 1; > > >> +} > > >> + > > >> static void meson_plane_atomic_update(struct drm_plane *plane, > > >> struct drm_plane_state *old_state) > > >> { > > > > [...] > > > > >> > > >> +static bool meson_plane_format_mod_supported(struct drm_plane *plane, > > >> + u32 format, u64 modifier) > > >> +{ > > >> + struct meson_plane *meson_plane = to_meson_plane(plane); > > >> + struct meson_drm *priv = meson_plane->priv; > > >> + int i; > > >> + > > >> + if (modifier == DRM_FORMAT_MOD_INVALID) > > >> + return false; > > >> + > > >> + if (modifier == DRM_FORMAT_MOD_LINEAR) > > >> + return true; > > >> + > > >> + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) && > > >> + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > > >> + return false; > > >> + > > >> + if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) > > >> + return false; > > >> + > > >> + for (i = 0 ; i < plane->modifier_count ; ++i) > > >> + if (plane->modifiers[i] == modifier) > > >> + break; > > >> + > > >> + if (i == plane->modifier_count) { > > >> + DRM_DEBUG_KMS("Unsupported modifier\n"); > > >> + return false; > > >> + } > > > > I can add a warn_once here, would it be enough ? > > > > >> + > > >> + if (priv->afbcd.ops && priv->afbcd.ops->supported_fmt) > > >> + return priv->afbcd.ops->supported_fmt(modifier, format); > > >> + > > >> + DRM_DEBUG_KMS("AFBC Unsupported\n"); > > >> + return false; > > >> +} > > >> + > > >> static const struct drm_plane_funcs meson_plane_funcs = { > > >> .update_plane = drm_atomic_helper_update_plane, > > >> .disable_plane = drm_atomic_helper_disable_plane, > > >> @@ -353,6 +457,7 @@ static const struct drm_plane_funcs meson_plane_funcs = { > > >> .reset = drm_atomic_helper_plane_reset, > > >> .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, > > >> .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, > > >> + .format_mod_supported = meson_plane_format_mod_supported, > > >> }; > > >> > > >> static const uint32_t supported_drm_formats[] = { > > >> @@ -364,10 +469,53 @@ static const uint32_t supported_drm_formats[] = { > > >> DRM_FORMAT_RGB565, > > >> }; > > >> > > >> +static const uint64_t format_modifiers_afbc_gxm[] = { > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_YTR), > > >> + /* SPLIT mandates SPARSE, RGB modes mandates YTR */ > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_SPLIT), > > >> + DRM_FORMAT_MOD_LINEAR, > > >> + DRM_FORMAT_MOD_INVALID, > > >> +}; > > >> + > > >> +static const uint64_t format_modifiers_afbc_g12a[] = { > > >> + /* > > >> + * - TOFIX Support AFBC modifiers for YUV formats (16x16 + TILED) > > >> + * - AFBC_FORMAT_MOD_YTR is mandatory since we only support RGB > > >> + * - SPLIT is mandatory for performances reasons when in 16x16 > > >> + * block size > > >> + * - 32x8 block size + SPLIT is mandatory with 4K frame size > > >> + * for performances reasons > > >> + */ > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_SPLIT), > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE), > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_SPLIT), > > >> + DRM_FORMAT_MOD_LINEAR, > > >> + DRM_FORMAT_MOD_INVALID, > > >> +}; > > >> + > > >> +static const uint64_t format_modifiers_default[] = { > > >> + DRM_FORMAT_MOD_LINEAR, > > >> + DRM_FORMAT_MOD_INVALID, > > >> +}; > > >> + > > >> int meson_plane_create(struct meson_drm *priv) > > >> { > > >> struct meson_plane *meson_plane; > > >> struct drm_plane *plane; > > >> + const uint64_t *format_modifiers = format_modifiers_default; > > >> > > >> meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), > > >> GFP_KERNEL); > > >> @@ -377,11 +525,16 @@ int meson_plane_create(struct meson_drm *priv) > > >> meson_plane->priv = priv; > > >> plane = &meson_plane->base; > > >> > > >> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) > > >> + format_modifiers = format_modifiers_afbc_gxm; > > >> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > > >> + format_modifiers = format_modifiers_afbc_g12a; > > >> + > > >> drm_universal_plane_init(priv->drm, plane, 0xFF, > > >> &meson_plane_funcs, > > >> supported_drm_formats, > > >> ARRAY_SIZE(supported_drm_formats), > > >> - NULL, > > >> + format_modifiers, > > >> DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); > > >> > > >> drm_plane_helper_add(plane, &meson_plane_helper_funcs); > > >> -- > > >> 2.22.0 > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane Date: Fri, 11 Oct 2019 09:46:01 +0200 Message-ID: References: <20191010092526.10419-1-narmstrong@baylibre.com> <20191010092526.10419-5-narmstrong@baylibre.com> <20191010132601.GA10110@arm.com> <44f1771f-d640-f23d-995f-7bfcadd213bc@baylibre.com> <20191010173152.GA575@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-ot1-x343.google.com (mail-ot1-x343.google.com [IPv6:2607:f8b0:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1107F6EBC0 for ; Fri, 11 Oct 2019 07:46:14 +0000 (UTC) Received: by mail-ot1-x343.google.com with SMTP id o44so7165449ota.10 for ; Fri, 11 Oct 2019 00:46:14 -0700 (PDT) In-Reply-To: <20191010173152.GA575@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Ayan Halder Cc: Neil Armstrong , "khilman@baylibre.com" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" , nd , "linux-arm-kernel@lists.infradead.org" List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBPY3QgMTAsIDIwMTkgYXQgNzozMiBQTSBBeWFuIEhhbGRlciA8QXlhbi5IYWxkZXJA YXJtLmNvbT4gd3JvdGU6Cj4KPiBPbiBUaHUsIE9jdCAxMCwgMjAxOSBhdCAwMzo0MToxNVBNICsw MjAwLCBOZWlsIEFybXN0cm9uZyB3cm90ZToKPiA+IEhpIEF5YW4sCj4gPgo+ID4gT24gMTAvMTAv MjAxOSAxNToyNiwgQXlhbiBIYWxkZXIgd3JvdGU6Cj4gPiA+IE9uIFRodSwgT2N0IDEwLCAyMDE5 IGF0IDExOjI1OjIzQU0gKzAyMDAsIE5laWwgQXJtc3Ryb25nIHdyb3RlOgo+ID4gPj4gVGhpcyBh ZGRzIGFsbCB0aGUgT1NEIGNvbmZpZ3VyYXRpb24gcGx1bWJpbmcgdG8gc3VwcG9ydCB0aGUgQUZC QyBkZWNvZGVycwo+ID4gPj4gcGF0aCB0byBkaXNwbGF5IG9mIHRoZSBPU0QxIHBsYW5lLgo+ID4g Pj4KPiA+ID4+IFRoZSBBbWxvZ2ljIEdYTSBhbmQgRzEyQSBBRkJDIGRlY29kZXJzIGFyZSBpbnRl Z3JhdGVkIHZlcnkgZGlmZmVyZW50bHkuCj4gPiA+Pgo+ID4gPj4gVGhlIEFtbG9naWMgR1hNIGhh cyBhIGRpcmVjdCBvdXRwdXQgcGF0aCB0byB0aGUgT1NEMSBWSVUgcGl4ZWwgaW5wdXQsCj4gPiA+ PiBiZWNhdXNlIHRoZSBHWE0gQUZCQyBkZWNvZGVyIHNlZW0gdG8gYmUgYSBjdXN0b20gSVAgZGV2 ZWxvcGVkIGJ5IEFtbG9naWMuCj4gPiA+Pgo+ID4gPj4gT24gdGhlIG90aGVyIHNpZGUsIHRoZSBB bWxvZ2ljIEcxMkEgQUZCQyBkZWNvZGVyIHNlZW1zIHRvIGJlIGFuIGV4dGVybmFsCj4gPiA+PiBJ UCB0aGF0IGVtaXQgcGl4ZWxzIG9uIGFuIEFYSSBtYXN0ZXIgaG9va2VkIHRvIGEgIk1hbGkgVW5w YWNrIiBibG9jawo+ID4gPj4gZmVlZGluZyB0aGUgT1NEMSBWSVUgcGl4ZWwgaW5wdXQuCj4gPiA+ PiBUaGlzIHVzZXMgYSB3ZWlyZCAiMHgxMDAwMDAwIiBpbnRlcm5hbCBIVyBwaHlzaWNhbCBhZGRy ZXNzIG9uIGJvdGgKPiA+ID4+IHNpZGVzIHRvIHRyYW5zZmVyIHRoZSBwaXhlbHMuCj4gPiA+Pgo+ ID4gPj4gRm9yIEFtbG9naWMgR1hNLCB0aGUgc3VwcG9ydGVkIHBpeGVsIGZvcm1hdHMgYXJlIHRo ZSBzYW1lIGFzIHRoZSBub3JtYWwKPiA+ID4+IGxpbmVhciBPU0QxIG1vZGUuCj4gPiA+Pgo+ID4g Pj4gT24gdGhlIG90aGVyIHNpZGUsIEFtbG9naWMgYWRkZWQgc3VwcG9ydCBmb3IgYWxsIEFGQkMg djEuMiBmb3JtYXRzIGZvcgo+ID4gPj4gdGhlIEcxMkEgQUZCQyBpbnRlZ3JhdGlvbi4KPiA+ID4+ Cj4gPiA+PiBGb3Igc2ltcGxpY2l0eSwgd2Ugc3RpY2sgdG8gdGhlIGFscmVhZHkgc3VwcG9ydGVk IGZvcm1hdHMgZm9yIG5vdy4KPiA+ID4+Cj4gPiA+PiBTaWduZWQtb2ZmLWJ5OiBOZWlsIEFybXN0 cm9uZyA8bmFybXN0cm9uZ0BiYXlsaWJyZS5jb20+Cj4gPiA+PiAtLS0KPiA+ID4+ICBkcml2ZXJz L2dwdS9kcm0vbWVzb24vbWVzb25fY3J0Yy5jICB8ICAgMiArCj4gPiA+PiAgZHJpdmVycy9ncHUv ZHJtL21lc29uL21lc29uX2Rydi5oICAgfCAgIDQgKwo+ID4gPj4gIGRyaXZlcnMvZ3B1L2RybS9t ZXNvbi9tZXNvbl9wbGFuZS5jIHwgMjE1ICsrKysrKysrKysrKysrKysrKysrKysrKy0tLS0KPiA+ ID4+ICAzIGZpbGVzIGNoYW5nZWQsIDE5MCBpbnNlcnRpb25zKCspLCAzMSBkZWxldGlvbnMoLSkK PiA+ID4+Cj4gPiA+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX2Ny dGMuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl9jcnRjLmMKPiA+ID4+IGluZGV4IDU3 YWUxYzEzZDFlNi4uZDQ3OGZhMjMyOTUxIDEwMDY0NAo+ID4gPj4gLS0tIGEvZHJpdmVycy9ncHUv ZHJtL21lc29uL21lc29uX2NydGMuYwo+ID4gPj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX2NydGMuYwo+ID4gPj4gQEAgLTI4MSw2ICsyODEsOCBAQCB2b2lkIG1lc29uX2NydGNf aXJxKHN0cnVjdCBtZXNvbl9kcm0gKnByaXYpCj4gPiA+PiAgICBpZiAocHJpdi0+dml1Lm9zZDFf ZW5hYmxlZCAmJiBwcml2LT52aXUub3NkMV9jb21taXQpIHsKPiA+ID4+ICAgICAgICAgICAgd3Jp dGVsX3JlbGF4ZWQocHJpdi0+dml1Lm9zZDFfY3RybF9zdGF0LAo+ID4gPj4gICAgICAgICAgICAg ICAgICAgICAgICAgICAgcHJpdi0+aW9fYmFzZSArIF9SRUcoVklVX09TRDFfQ1RSTF9TVEFUKSk7 Cj4gPiA+PiArICAgICAgICAgIHdyaXRlbF9yZWxheGVkKHByaXYtPnZpdS5vc2QxX2N0cmxfc3Rh dDIsCj4gPiA+PiArICAgICAgICAgICAgICAgICAgICAgICAgICBwcml2LT5pb19iYXNlICsgX1JF RyhWSVVfT1NEMV9DVFJMX1NUQVQyKSk7Cj4gPiA+PiAgICAgICAgICAgIHdyaXRlbF9yZWxheGVk KHByaXYtPnZpdS5vc2QxX2JsazBfY2ZnWzBdLAo+ID4gPj4gICAgICAgICAgICAgICAgICAgICAg ICAgICAgcHJpdi0+aW9fYmFzZSArIF9SRUcoVklVX09TRDFfQkxLMF9DRkdfVzApKTsKPiA+ID4+ ICAgICAgICAgICAgd3JpdGVsX3JlbGF4ZWQocHJpdi0+dml1Lm9zZDFfYmxrMF9jZmdbMV0sCj4g PiA+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX2Rydi5oIGIvZHJp dmVycy9ncHUvZHJtL21lc29uL21lc29uX2Rydi5oCj4gPiA+PiBpbmRleCA2MGYxM2M2ZjM0ZTUu LmRlMjUzNDliZThhYSAxMDA2NDQKPiA+ID4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9t ZXNvbl9kcnYuaAo+ID4gPj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX2Rydi5o Cj4gPiA+PiBAQCAtNTMsOCArNTMsMTIgQEAgc3RydWN0IG1lc29uX2RybSB7Cj4gPiA+PiAgICAg ICAgICAgIGJvb2wgb3NkMV9lbmFibGVkOwo+ID4gPj4gICAgICAgICAgICBib29sIG9zZDFfaW50 ZXJsYWNlOwo+ID4gPj4gICAgICAgICAgICBib29sIG9zZDFfY29tbWl0Owo+ID4gPj4gKyAgICAg ICAgICBib29sIG9zZDFfYWZiY2Q7Cj4gPiA+PiAgICAgICAgICAgIHVpbnQzMl90IG9zZDFfY3Ry bF9zdGF0Owo+ID4gPj4gKyAgICAgICAgICB1aW50MzJfdCBvc2QxX2N0cmxfc3RhdDI7Cj4gPiA+ PiAgICAgICAgICAgIHVpbnQzMl90IG9zZDFfYmxrMF9jZmdbNV07Cj4gPiA+PiArICAgICAgICAg IHVpbnQzMl90IG9zZDFfYmxrMV9jZmc0Owo+ID4gPj4gKyAgICAgICAgICB1aW50MzJfdCBvc2Qx X2JsazJfY2ZnNDsKPiA+ID4+ICAgICAgICAgICAgdWludDMyX3Qgb3NkMV9hZGRyOwo+ID4gPj4g ICAgICAgICAgICB1aW50MzJfdCBvc2QxX3N0cmlkZTsKPiA+ID4+ICAgICAgICAgICAgdWludDMy X3Qgb3NkMV9oZWlnaHQ7Cj4gPiA+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3BsYW5lLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fcGxhbmUuYwo+ID4g Pj4gaW5kZXggNWU3OThjMjc2MDM3Li40MTI5NDFhYTg0MDIgMTAwNjQ0Cj4gPiA+PiAtLS0gYS9k cml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fcGxhbmUuYwo+ID4gPj4gKysrIGIvZHJpdmVycy9n cHUvZHJtL21lc29uL21lc29uX3BsYW5lLmMKPiA+ID4+IEBAIC0yMyw2ICsyMyw3IEBACj4gPiA+ PiAgI2luY2x1ZGUgIm1lc29uX3BsYW5lLmgiCj4gPiA+PiAgI2luY2x1ZGUgIm1lc29uX3JlZ2lz dGVycy5oIgo+ID4gPj4gICNpbmNsdWRlICJtZXNvbl92aXUuaCIKPiA+ID4+ICsjaW5jbHVkZSAi bWVzb25fb3NkX2FmYmNkLmgiCj4gPiA+Pgo+ID4gPj4gIC8qIE9TRF9TQ0lfV0hfTTEgKi8KPiA+ ID4+ICAjZGVmaW5lIFNDSV9XSF9NMV9XKHcpICAgICAgICAgICAgICAgICAgICBGSUVMRF9QUkVQ KEdFTk1BU0soMjgsIDE2KSwgdykKPiA+ID4+IEBAIC05MiwxMiArOTMsMzggQEAgc3RhdGljIGlu dCBtZXNvbl9wbGFuZV9hdG9taWNfY2hlY2soc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsCj4gPiA+ PiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZmFsc2UsIHRy dWUpOwo+ID4gPj4gIH0KPiA+ID4+Cj4gPiA+PiArI2RlZmluZSBNRVNPTl9NT0RfQUZCQ19WQUxJ RF9CSVRTIChBRkJDX0ZPUk1BVF9NT0RfQkxPQ0tfU0laRV8xNngxNiB8ICAgICBcCj4gPiA+PiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBBRkJDX0ZPUk1BVF9NT0RfQkxPQ0tfU0laRV8z Mng4IHwgICAgXAo+ID4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgQUZCQ19GT1JN QVRfTU9EX1lUUiB8ICAgICAgICAgICAgICAgIFwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIEFGQkNfRk9STUFUX01PRF9TUEFSU0UgfCAgICAgICAgICAgICBcCj4gPiA+PiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBBRkJDX0ZPUk1BVF9NT0RfU1BMSVQpCj4gPiA+ PiArCj4gPiA+PiAgLyogVGFrZXMgYSBmaXhlZCAxNi4xNiBudW1iZXIgYW5kIGNvbnZlcnRzIGl0 IHRvIGludGVnZXIuICovCj4gPiA+PiAgc3RhdGljIGlubGluZSBpbnQ2NF90IGZpeGVkMTZfdG9f aW50KGludDY0X3QgdmFsdWUpCj4gPiA+PiAgewo+ID4gPj4gICAgcmV0dXJuIHZhbHVlID4+IDE2 Owo+ID4gPj4gIH0KPiA+ID4+Cj4gPiA+PiArc3RhdGljIHUzMiBtZXNvbl9nMTJhX2FmYmNkX2xp bmVfc3RyaWRlKHN0cnVjdCBtZXNvbl9kcm0gKnByaXYpCj4gPiA+PiArewo+ID4gPj4gKyAgdTMy IGxpbmVfc3RyaWRlID0gMDsKPiA+ID4+ICsKPiA+ID4+ICsgIHN3aXRjaCAocHJpdi0+YWZiY2Qu Zm9ybWF0KSB7Cj4gPiA+PiArICBjYXNlIERSTV9GT1JNQVRfUkdCNTY1Ogo+ID4gPj4gKyAgICAg ICAgICBsaW5lX3N0cmlkZSA9ICgocHJpdi0+dml1Lm9zZDFfd2lkdGggPDwgNCkgKyAxMjcpID4+ IDc7Cj4gPiA+PiArICAgICAgICAgIGJyZWFrOwo+ID4gPj4gKyAgY2FzZSBEUk1fRk9STUFUX1JH Qjg4ODoKPiA+ID4+ICsgIGNhc2UgRFJNX0ZPUk1BVF9YUkdCODg4ODoKPiA+ID4+ICsgIGNhc2Ug RFJNX0ZPUk1BVF9BUkdCODg4ODoKPiA+ID4+ICsgIGNhc2UgRFJNX0ZPUk1BVF9YQkdSODg4ODoK PiA+ID4+ICsgIGNhc2UgRFJNX0ZPUk1BVF9BQkdSODg4ODoKPiA+ID4gUGxlYXNlIGhhdmUgYSBs b29rIGF0Cj4gPiA+IGh0dHBzOi8vd3d3Lmtlcm5lbC5vcmcvZG9jL2h0bWwvbGF0ZXN0L2dwdS9h ZmJjLmh0bWwgZm9yIG91cgo+ID4gPiByZWNvbW1lbmRhdGlvbi4gV2Ugc3VnZ2VzdCB0aGF0ICpY KiBmb3JtYXRzIGFyZSBhdm9pZGVkLgo+ID4gPgo+ID4gPiBBbHNvLCBmb3IgaW50ZXJvcGVyYWJp bGl0eSBhbmQgbWF4aW11bSBjb21wcmVzc2lvbiBlZmZpY2llbmN5ICh3aXRoCj4gPiA+IEFGQkNf Rk9STUFUX01PRF9ZVFIpLCB3ZSBzdWdnZXN0IHRoZSBmb2xsb3dpbmcgb3JkZXIgOi0KPiA+ID4K PiA+ID4gICAgICAgICBDb21wb25lbnQgMDogUgo+ID4gPiAgICAgICAgIENvbXBvbmVudCAxOiBH Cj4gPiA+ICAgICAgICAgQ29tcG9uZW50IDI6IEIKPiA+ID4gICAgICAgICBDb21wb25lbnQgMzog QSAoaWYgYXZhaWxhYmxlKQo+ID4KPiA+Cj4gPiBTb3JyeSBJIGRvbid0IHVuZGVyc3RhbmQsIHlv dSBhc2sgbWUgdG8gbGltaXQgQUZCQyB0byBBQkdSODg4OCA/Cj4KPiBBcG9sb2dpZXMgZm9yIHRo ZSBjb25mdXNpb24sIGFzIHBlciB0aGUgbGluaywgdGhlIGZvcm1hdHMgd2hpY2ggYXJlCj4gc3Vn Z2VzdGVkIHdpdGggQUZCQ19GT1JNQVRfTU9EX1lUUiBhcmUgdGhlIEJHUi9BQkdSIGZvcm1hdHMg KGFzCj4gbGlzdGVkIGluIHRoZSAnQUZCQyBmb3JtYXRzJyB0YWJsZSkKPgo+IFRodXMsIGFueSBv dGhlciBwZXJtdXRhdGlvbiBvZiB0aGUgY29tcG9uZW50cyBtaWdodCBtYWtlIGl0IGluY29tcGF0 aWJsZQo+IHdpdGggc29tZSBvdGhlciBBRkJDIHByb2R1Y2Vycy9jb25zdW1lcnMuCgpVaCwgdGhh dCdzIG5vdCBob3cgdGhpcyBpcyBzdXBwb3NlZCB0byBiZSB1c2VkLiBEcml2ZXJzIGFyZSBtZWFu dCB0bwpleHBvc2UgX2V2ZXJ5dGhpbmdfIHRoZXkgc3VwcG9ydCAoYm9udXMgaWYgeW91IHJvdWdo bHkgc29ydCBpdCBpbgpwcmVmZXJlbmNlIG9yZGVyKS4gVXNlcnNwYWNlIHRoZW4gY29tcHV0ZXMg dGhlIGludGVyc2VjdGlvbiBvZgptb2RpZmllcnMvZm9ybWF0cyBzdXBwb3J0ZWQgYnkgYWxsIGRl dmljZXMgaXQgbmVlZHMgdG8gc2hhcmUgYSBidWZmZXIKd2l0aC4gQWxsb3dpbmcgdGhhdCB3YXMg dGhlIGVudGlyZSBwb2ludCBvZiBtb2RpZmllcnMsIGlmIHdlCmFydGlmaWNpYWxseSBsaW1pdCB0 byB0aGUgY29tbW9uIGRlbm9taW5hdG9yIHdlJ3JlIGJhY2sgIm9ubHkgbGluZWFyCndvcmtzIGV2 ZXJ5d2hlcmUiLgotRGFuaWVsCgo+Cj4gPgo+ID4gQnV0IHdoeSBpZiB0aGUgSFcgKEdQVSBhbmQg RFBVKSBpcyBjYXBhYmxlIG9mID8KPiA+Cj4gPiBJc24ndCBpdCBhbiB1c2Vyc3BhY2UgY2hvaWNl ID8gSSB1bmRlcnN0YW5kIFhSR0I4ODg4IGlzIGEgd2FzdGUKPiA+IG9mIG1lbW9yeSBzcGFjZSBh bmQgY29tcHJlc3Npb24gZWZmaWNpZW5jeSwgYnV0IHRoaXMgaXMgbm90IHRoZQo+ID4ga2VybmVs IGRyaXZlcidzIHRvIGRlY2lkZSB0aGlzLCByaWdodCA/Cj4gSXQgaXMgYSByZWNjb21lbmRhdGlv biBieSB0aGUgQUZCQyBzcGVjLiBBcyBmYXIgYXMgSSB1bmRlcnN0YW5kLCBpdAo+IGRlcGVuZHMg dXBvbiB0aGUgaW1wbGVtZW50b3Igb2YgdGhlIEFGQkMgc3BlYyhpZSBkcHUsIGdwdSwgdnB1LCBl dGMpCj4gdG8gYWxsb3cvZGlzYWxsb3cgKlgqIGZvcm1hdHMgZm9yIEFGQkMgZW5jb2RpbmcvZGVj b2RpbmcuCj4KPiA+Cj4gPiBGb3IgaW50ZXJvcGVyYWJpbGl0eSBJJ2xsIHVuZGVyc3RhbmQgcmVj b21tZW5kaW5nIGEgbWluaW1hbCBzZXQKPiA+IG9mIG1vZGlmaWVycyBhbmQgZm9ybWF0cy4gQnV0 IGhlcmUsIGVhY2ggcGxhdGZvcm0gaXMgYWxzbyBsaW1pdGVkCj4gPiBieSBpdCdzIEdQVSBjYXBh YmlsaXRlcyBhc3dlbGwuCj4gQWdyZWVkCj4KPiA+Cj4gPiBMaW1pdGluZyB0byBBQkdSODg4OCB3 b3VsZCBkaXNjYXJkIGxpa2UgZXZlcnkgbm9uLUFuZHJvaWQgcmVuZGVyZXJzLAo+ID4gdXNpbmcg QUZCQywgSSdtIG5vdCBzdXJlIGl0J3MgdGhlIGtlcm5lbHMgZHJpdmVyJ3MgcmVzcG9uc2liaWxp dHkuCj4gSSBhbSBub3QgZmFtaWxpYXIgd2l0aCBub24tQW5kcm9pZCByZW5kZXJlcnMuCj4gPgo+ ID4gPgo+ID4gPiBUaHVzLCBEUk1fRk9STUFUX0FCR1IsIERSTV9GT1JNQVRfQkdSIHNob3VsZCBv bmx5IGJlIGFsbG93ZWQuCj4gPiA+PiArICAgICAgICAgIGxpbmVfc3RyaWRlID0gKChwcml2LT52 aXUub3NkMV93aWR0aCA8PCA1KSArIDEyNykgPj4gNzsKPiA+ID4+ICsgICAgICAgICAgYnJlYWs7 Cj4gPiA+PiArICB9Cj4gPiA+PiArCj4gPiA+PiArICByZXR1cm4gKChsaW5lX3N0cmlkZSArIDEp ID4+IDEpIDw8IDE7Cj4gPiA+PiArfQo+ID4gPj4gKwo+ID4gPj4gIHN0YXRpYyB2b2lkIG1lc29u X3BsYW5lX2F0b21pY191cGRhdGUoc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsCj4gPiA+PiAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3QgZHJtX3BsYW5lX3N0YXRlICpvbGRf c3RhdGUpCj4gPiA+PiAgewo+ID4KPiA+IFsuLi5dCj4gPgo+ID4gPj4KPiA+ID4+ICtzdGF0aWMg Ym9vbCBtZXNvbl9wbGFuZV9mb3JtYXRfbW9kX3N1cHBvcnRlZChzdHJ1Y3QgZHJtX3BsYW5lICpw bGFuZSwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB1MzIg Zm9ybWF0LCB1NjQgbW9kaWZpZXIpCj4gPiA+PiArewo+ID4gPj4gKyAgc3RydWN0IG1lc29uX3Bs YW5lICptZXNvbl9wbGFuZSA9IHRvX21lc29uX3BsYW5lKHBsYW5lKTsKPiA+ID4+ICsgIHN0cnVj dCBtZXNvbl9kcm0gKnByaXYgPSBtZXNvbl9wbGFuZS0+cHJpdjsKPiA+ID4+ICsgIGludCBpOwo+ ID4gPj4gKwo+ID4gPj4gKyAgaWYgKG1vZGlmaWVyID09IERSTV9GT1JNQVRfTU9EX0lOVkFMSUQp Cj4gPiA+PiArICAgICAgICAgIHJldHVybiBmYWxzZTsKPiA+ID4+ICsKPiA+ID4+ICsgIGlmICht b2RpZmllciA9PSBEUk1fRk9STUFUX01PRF9MSU5FQVIpCj4gPiA+PiArICAgICAgICAgIHJldHVy biB0cnVlOwo+ID4gPj4gKwo+ID4gPj4gKyAgaWYgKCFtZXNvbl92cHVfaXNfY29tcGF0aWJsZShw cml2LCBWUFVfQ09NUEFUSUJMRV9HWE0pICYmCj4gPiA+PiArICAgICAgIW1lc29uX3ZwdV9pc19j b21wYXRpYmxlKHByaXYsIFZQVV9DT01QQVRJQkxFX0cxMkEpKQo+ID4gPj4gKyAgICAgICAgICBy ZXR1cm4gZmFsc2U7Cj4gPiA+PiArCj4gPiA+PiArICBpZiAobW9kaWZpZXIgJiB+RFJNX0ZPUk1B VF9NT0RfQVJNX0FGQkMoTUVTT05fTU9EX0FGQkNfVkFMSURfQklUUykpCj4gPiA+PiArICAgICAg ICAgIHJldHVybiBmYWxzZTsKPiA+ID4+ICsKPiA+ID4+ICsgIGZvciAoaSA9IDAgOyBpIDwgcGxh bmUtPm1vZGlmaWVyX2NvdW50IDsgKytpKQo+ID4gPj4gKyAgICAgICAgICBpZiAocGxhbmUtPm1v ZGlmaWVyc1tpXSA9PSBtb2RpZmllcikKPiA+ID4+ICsgICAgICAgICAgICAgICAgICBicmVhazsK PiA+ID4+ICsKPiA+ID4+ICsgIGlmIChpID09IHBsYW5lLT5tb2RpZmllcl9jb3VudCkgewo+ID4g Pj4gKyAgICAgICAgICBEUk1fREVCVUdfS01TKCJVbnN1cHBvcnRlZCBtb2RpZmllclxuIik7Cj4g PiA+PiArICAgICAgICAgIHJldHVybiBmYWxzZTsKPiA+ID4+ICsgIH0KPiA+Cj4gPiBJIGNhbiBh ZGQgYSB3YXJuX29uY2UgaGVyZSwgd291bGQgaXQgYmUgZW5vdWdoID8KPiA+Cj4gPiA+PiArCj4g PiA+PiArICBpZiAocHJpdi0+YWZiY2Qub3BzICYmIHByaXYtPmFmYmNkLm9wcy0+c3VwcG9ydGVk X2ZtdCkKPiA+ID4+ICsgICAgICAgICAgcmV0dXJuIHByaXYtPmFmYmNkLm9wcy0+c3VwcG9ydGVk X2ZtdChtb2RpZmllciwgZm9ybWF0KTsKPiA+ID4+ICsKPiA+ID4+ICsgIERSTV9ERUJVR19LTVMo IkFGQkMgVW5zdXBwb3J0ZWRcbiIpOwo+ID4gPj4gKyAgcmV0dXJuIGZhbHNlOwo+ID4gPj4gK30K PiA+ID4+ICsKPiA+ID4+ICBzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9wbGFuZV9mdW5jcyBtZXNv bl9wbGFuZV9mdW5jcyA9IHsKPiA+ID4+ICAgIC51cGRhdGVfcGxhbmUgICAgICAgICAgID0gZHJt X2F0b21pY19oZWxwZXJfdXBkYXRlX3BsYW5lLAo+ID4gPj4gICAgLmRpc2FibGVfcGxhbmUgICAg ICAgICAgPSBkcm1fYXRvbWljX2hlbHBlcl9kaXNhYmxlX3BsYW5lLAo+ID4gPj4gQEAgLTM1Myw2 ICs0NTcsNyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9wbGFuZV9mdW5jcyBtZXNvbl9wbGFu ZV9mdW5jcyA9IHsKPiA+ID4+ICAgIC5yZXNldCAgICAgICAgICAgICAgICAgID0gZHJtX2F0b21p Y19oZWxwZXJfcGxhbmVfcmVzZXQsCj4gPiA+PiAgICAuYXRvbWljX2R1cGxpY2F0ZV9zdGF0ZSA9 IGRybV9hdG9taWNfaGVscGVyX3BsYW5lX2R1cGxpY2F0ZV9zdGF0ZSwKPiA+ID4+ICAgIC5hdG9t aWNfZGVzdHJveV9zdGF0ZSAgID0gZHJtX2F0b21pY19oZWxwZXJfcGxhbmVfZGVzdHJveV9zdGF0 ZSwKPiA+ID4+ICsgIC5mb3JtYXRfbW9kX3N1cHBvcnRlZCAgID0gbWVzb25fcGxhbmVfZm9ybWF0 X21vZF9zdXBwb3J0ZWQsCj4gPiA+PiAgfTsKPiA+ID4+Cj4gPiA+PiAgc3RhdGljIGNvbnN0IHVp bnQzMl90IHN1cHBvcnRlZF9kcm1fZm9ybWF0c1tdID0gewo+ID4gPj4gQEAgLTM2NCwxMCArNDY5 LDUzIEBAIHN0YXRpYyBjb25zdCB1aW50MzJfdCBzdXBwb3J0ZWRfZHJtX2Zvcm1hdHNbXSA9IHsK PiA+ID4+ICAgIERSTV9GT1JNQVRfUkdCNTY1LAo+ID4gPj4gIH07Cj4gPiA+Pgo+ID4gPj4gK3N0 YXRpYyBjb25zdCB1aW50NjRfdCBmb3JtYXRfbW9kaWZpZXJzX2FmYmNfZ3htW10gPSB7Cj4gPiA+ PiArICBEUk1fRk9STUFUX01PRF9BUk1fQUZCQyhBRkJDX0ZPUk1BVF9NT0RfQkxPQ0tfU0laRV8x NngxNiB8Cj4gPiA+PiArICAgICAgICAgICAgICAgICAgICAgICAgICBBRkJDX0ZPUk1BVF9NT0Rf U1BBUlNFIHwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgIEFGQkNfRk9STUFUX01P RF9ZVFIpLAo+ID4gPj4gKyAgLyogU1BMSVQgbWFuZGF0ZXMgU1BBUlNFLCBSR0IgbW9kZXMgbWFu ZGF0ZXMgWVRSICovCj4gPiA+PiArICBEUk1fRk9STUFUX01PRF9BUk1fQUZCQyhBRkJDX0ZPUk1B VF9NT0RfQkxPQ0tfU0laRV8xNngxNiB8Cj4gPiA+PiArICAgICAgICAgICAgICAgICAgICAgICAg ICBBRkJDX0ZPUk1BVF9NT0RfWVRSIHwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAgICAgICAg IEFGQkNfRk9STUFUX01PRF9TUEFSU0UgfAo+ID4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgQUZCQ19GT1JNQVRfTU9EX1NQTElUKSwKPiA+ID4+ICsgIERSTV9GT1JNQVRfTU9EX0xJTkVB UiwKPiA+ID4+ICsgIERSTV9GT1JNQVRfTU9EX0lOVkFMSUQsCj4gPiA+PiArfTsKPiA+ID4+ICsK PiA+ID4+ICtzdGF0aWMgY29uc3QgdWludDY0X3QgZm9ybWF0X21vZGlmaWVyc19hZmJjX2cxMmFb XSA9IHsKPiA+ID4+ICsgIC8qCj4gPiA+PiArICAgKiAtIFRPRklYIFN1cHBvcnQgQUZCQyBtb2Rp ZmllcnMgZm9yIFlVViBmb3JtYXRzICgxNngxNiArIFRJTEVEKQo+ID4gPj4gKyAgICogLSBBRkJD X0ZPUk1BVF9NT0RfWVRSIGlzIG1hbmRhdG9yeSBzaW5jZSB3ZSBvbmx5IHN1cHBvcnQgUkdCCj4g PiA+PiArICAgKiAtIFNQTElUIGlzIG1hbmRhdG9yeSBmb3IgcGVyZm9ybWFuY2VzIHJlYXNvbnMg d2hlbiBpbiAxNngxNgo+ID4gPj4gKyAgICogICBibG9jayBzaXplCj4gPiA+PiArICAgKiAtIDMy eDggYmxvY2sgc2l6ZSArIFNQTElUIGlzIG1hbmRhdG9yeSB3aXRoIDRLIGZyYW1lIHNpemUKPiA+ ID4+ICsgICAqICAgZm9yIHBlcmZvcm1hbmNlcyByZWFzb25zCj4gPiA+PiArICAgKi8KPiA+ID4+ ICsgIERSTV9GT1JNQVRfTU9EX0FSTV9BRkJDKEFGQkNfRk9STUFUX01PRF9CTE9DS19TSVpFXzE2 eDE2IHwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgIEFGQkNfRk9STUFUX01PRF9Z VFIgfAo+ID4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgQUZCQ19GT1JNQVRfTU9EX1NQ QVJTRSB8Cj4gPiA+PiArICAgICAgICAgICAgICAgICAgICAgICAgICBBRkJDX0ZPUk1BVF9NT0Rf U1BMSVQpLAo+ID4gPj4gKyAgRFJNX0ZPUk1BVF9NT0RfQVJNX0FGQkMoQUZCQ19GT1JNQVRfTU9E X0JMT0NLX1NJWkVfMzJ4OCB8Cj4gPiA+PiArICAgICAgICAgICAgICAgICAgICAgICAgICBBRkJD X0ZPUk1BVF9NT0RfWVRSIHwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgIEFGQkNf Rk9STUFUX01PRF9TUEFSU0UpLAo+ID4gPj4gKyAgRFJNX0ZPUk1BVF9NT0RfQVJNX0FGQkMoQUZC Q19GT1JNQVRfTU9EX0JMT0NLX1NJWkVfMzJ4OCB8Cj4gPiA+PiArICAgICAgICAgICAgICAgICAg ICAgICAgICBBRkJDX0ZPUk1BVF9NT0RfWVRSIHwKPiA+ID4+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgIEFGQkNfRk9STUFUX01PRF9TUEFSU0UgfAo+ID4gPj4gKyAgICAgICAgICAgICAgICAg ICAgICAgICAgQUZCQ19GT1JNQVRfTU9EX1NQTElUKSwKPiA+ID4+ICsgIERSTV9GT1JNQVRfTU9E X0xJTkVBUiwKPiA+ID4+ICsgIERSTV9GT1JNQVRfTU9EX0lOVkFMSUQsCj4gPiA+PiArfTsKPiA+ ID4+ICsKPiA+ID4+ICtzdGF0aWMgY29uc3QgdWludDY0X3QgZm9ybWF0X21vZGlmaWVyc19kZWZh dWx0W10gPSB7Cj4gPiA+PiArICBEUk1fRk9STUFUX01PRF9MSU5FQVIsCj4gPiA+PiArICBEUk1f Rk9STUFUX01PRF9JTlZBTElELAo+ID4gPj4gK307Cj4gPiA+PiArCj4gPiA+PiAgaW50IG1lc29u X3BsYW5lX2NyZWF0ZShzdHJ1Y3QgbWVzb25fZHJtICpwcml2KQo+ID4gPj4gIHsKPiA+ID4+ICAg IHN0cnVjdCBtZXNvbl9wbGFuZSAqbWVzb25fcGxhbmU7Cj4gPiA+PiAgICBzdHJ1Y3QgZHJtX3Bs YW5lICpwbGFuZTsKPiA+ID4+ICsgIGNvbnN0IHVpbnQ2NF90ICpmb3JtYXRfbW9kaWZpZXJzID0g Zm9ybWF0X21vZGlmaWVyc19kZWZhdWx0Owo+ID4gPj4KPiA+ID4+ICAgIG1lc29uX3BsYW5lID0g ZGV2bV9remFsbG9jKHByaXYtPmRybS0+ZGV2LCBzaXplb2YoKm1lc29uX3BsYW5lKSwKPiA+ID4+ ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEdGUF9LRVJORUwpOwo+ID4gPj4gQEAgLTM3 NywxMSArNTI1LDE2IEBAIGludCBtZXNvbl9wbGFuZV9jcmVhdGUoc3RydWN0IG1lc29uX2RybSAq cHJpdikKPiA+ID4+ICAgIG1lc29uX3BsYW5lLT5wcml2ID0gcHJpdjsKPiA+ID4+ICAgIHBsYW5l ID0gJm1lc29uX3BsYW5lLT5iYXNlOwo+ID4gPj4KPiA+ID4+ICsgIGlmIChtZXNvbl92cHVfaXNf Y29tcGF0aWJsZShwcml2LCBWUFVfQ09NUEFUSUJMRV9HWE0pKQo+ID4gPj4gKyAgICAgICAgICBm b3JtYXRfbW9kaWZpZXJzID0gZm9ybWF0X21vZGlmaWVyc19hZmJjX2d4bTsKPiA+ID4+ICsgIGVs c2UgaWYgKG1lc29uX3ZwdV9pc19jb21wYXRpYmxlKHByaXYsIFZQVV9DT01QQVRJQkxFX0cxMkEp KQo+ID4gPj4gKyAgICAgICAgICBmb3JtYXRfbW9kaWZpZXJzID0gZm9ybWF0X21vZGlmaWVyc19h ZmJjX2cxMmE7Cj4gPiA+PiArCj4gPiA+PiAgICBkcm1fdW5pdmVyc2FsX3BsYW5lX2luaXQocHJp di0+ZHJtLCBwbGFuZSwgMHhGRiwKPiA+ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAm bWVzb25fcGxhbmVfZnVuY3MsCj4gPiA+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgc3Vw cG9ydGVkX2RybV9mb3JtYXRzLAo+ID4gPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAgIEFS UkFZX1NJWkUoc3VwcG9ydGVkX2RybV9mb3JtYXRzKSwKPiA+ID4+IC0gICAgICAgICAgICAgICAg ICAgICAgICAgICBOVUxMLAo+ID4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgIGZvcm1h dF9tb2RpZmllcnMsCj4gPiA+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgRFJNX1BMQU5F X1RZUEVfUFJJTUFSWSwgIm1lc29uX3ByaW1hcnlfcGxhbmUiKTsKPiA+ID4+Cj4gPiA+PiAgICBk cm1fcGxhbmVfaGVscGVyX2FkZChwbGFuZSwgJm1lc29uX3BsYW5lX2hlbHBlcl9mdW5jcyk7Cj4g PiA+PiAtLQo+ID4gPj4gMi4yMi4wCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KPiBkcmktZGV2ZWwgbWFpbGluZyBsaXN0Cj4gZHJpLWRldmVsQGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4v bGlzdGluZm8vZHJpLWRldmVsCgoKCi0tIApEYW5pZWwgVmV0dGVyClNvZnR3YXJlIEVuZ2luZWVy LCBJbnRlbCBDb3Jwb3JhdGlvbgorNDEgKDApIDc5IDM2NSA1NyA0OCAtIGh0dHA6Ly9ibG9nLmZm d2xsLmNoCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRy 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linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , "khilman@baylibre.com" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" , nd , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Thu, Oct 10, 2019 at 7:32 PM Ayan Halder wrote: > > On Thu, Oct 10, 2019 at 03:41:15PM +0200, Neil Armstrong wrote: > > Hi Ayan, > > > > On 10/10/2019 15:26, Ayan Halder wrote: > > > On Thu, Oct 10, 2019 at 11:25:23AM +0200, Neil Armstrong wrote: > > >> This adds all the OSD configuration plumbing to support the AFBC decoders > > >> path to display of the OSD1 plane. > > >> > > >> The Amlogic GXM and G12A AFBC decoders are integrated very differently. > > >> > > >> The Amlogic GXM has a direct output path to the OSD1 VIU pixel input, > > >> because the GXM AFBC decoder seem to be a custom IP developed by Amlogic. > > >> > > >> On the other side, the Amlogic G12A AFBC decoder seems to be an external > > >> IP that emit pixels on an AXI master hooked to a "Mali Unpack" block > > >> feeding the OSD1 VIU pixel input. > > >> This uses a weird "0x1000000" internal HW physical address on both > > >> sides to transfer the pixels. > > >> > > >> For Amlogic GXM, the supported pixel formats are the same as the normal > > >> linear OSD1 mode. > > >> > > >> On the other side, Amlogic added support for all AFBC v1.2 formats for > > >> the G12A AFBC integration. > > >> > > >> For simplicity, we stick to the already supported formats for now. > > >> > > >> Signed-off-by: Neil Armstrong > > >> --- > > >> drivers/gpu/drm/meson/meson_crtc.c | 2 + > > >> drivers/gpu/drm/meson/meson_drv.h | 4 + > > >> drivers/gpu/drm/meson/meson_plane.c | 215 ++++++++++++++++++++++++---- > > >> 3 files changed, 190 insertions(+), 31 deletions(-) > > >> > > >> diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c > > >> index 57ae1c13d1e6..d478fa232951 100644 > > >> --- a/drivers/gpu/drm/meson/meson_crtc.c > > >> +++ b/drivers/gpu/drm/meson/meson_crtc.c > > >> @@ -281,6 +281,8 @@ void meson_crtc_irq(struct meson_drm *priv) > > >> if (priv->viu.osd1_enabled && priv->viu.osd1_commit) { > > >> writel_relaxed(priv->viu.osd1_ctrl_stat, > > >> priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); > > >> + writel_relaxed(priv->viu.osd1_ctrl_stat2, > > >> + priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > > >> writel_relaxed(priv->viu.osd1_blk0_cfg[0], > > >> priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); > > >> writel_relaxed(priv->viu.osd1_blk0_cfg[1], > > >> diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h > > >> index 60f13c6f34e5..de25349be8aa 100644 > > >> --- a/drivers/gpu/drm/meson/meson_drv.h > > >> +++ b/drivers/gpu/drm/meson/meson_drv.h > > >> @@ -53,8 +53,12 @@ struct meson_drm { > > >> bool osd1_enabled; > > >> bool osd1_interlace; > > >> bool osd1_commit; > > >> + bool osd1_afbcd; > > >> uint32_t osd1_ctrl_stat; > > >> + uint32_t osd1_ctrl_stat2; > > >> uint32_t osd1_blk0_cfg[5]; > > >> + uint32_t osd1_blk1_cfg4; > > >> + uint32_t osd1_blk2_cfg4; > > >> uint32_t osd1_addr; > > >> uint32_t osd1_stride; > > >> uint32_t osd1_height; > > >> diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c > > >> index 5e798c276037..412941aa8402 100644 > > >> --- a/drivers/gpu/drm/meson/meson_plane.c > > >> +++ b/drivers/gpu/drm/meson/meson_plane.c > > >> @@ -23,6 +23,7 @@ > > >> #include "meson_plane.h" > > >> #include "meson_registers.h" > > >> #include "meson_viu.h" > > >> +#include "meson_osd_afbcd.h" > > >> > > >> /* OSD_SCI_WH_M1 */ > > >> #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w) > > >> @@ -92,12 +93,38 @@ static int meson_plane_atomic_check(struct drm_plane *plane, > > >> false, true); > > >> } > > >> > > >> +#define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \ > > >> + AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \ > > >> + AFBC_FORMAT_MOD_YTR | \ > > >> + AFBC_FORMAT_MOD_SPARSE | \ > > >> + AFBC_FORMAT_MOD_SPLIT) > > >> + > > >> /* Takes a fixed 16.16 number and converts it to integer. */ > > >> static inline int64_t fixed16_to_int(int64_t value) > > >> { > > >> return value >> 16; > > >> } > > >> > > >> +static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv) > > >> +{ > > >> + u32 line_stride = 0; > > >> + > > >> + switch (priv->afbcd.format) { > > >> + case DRM_FORMAT_RGB565: > > >> + line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7; > > >> + break; > > >> + case DRM_FORMAT_RGB888: > > >> + case DRM_FORMAT_XRGB8888: > > >> + case DRM_FORMAT_ARGB8888: > > >> + case DRM_FORMAT_XBGR8888: > > >> + case DRM_FORMAT_ABGR8888: > > > Please have a look at > > > https://www.kernel.org/doc/html/latest/gpu/afbc.html for our > > > recommendation. We suggest that *X* formats are avoided. > > > > > > Also, for interoperability and maximum compression efficiency (with > > > AFBC_FORMAT_MOD_YTR), we suggest the following order :- > > > > > > Component 0: R > > > Component 1: G > > > Component 2: B > > > Component 3: A (if available) > > > > > > Sorry I don't understand, you ask me to limit AFBC to ABGR8888 ? > > Apologies for the confusion, as per the link, the formats which are > suggested with AFBC_FORMAT_MOD_YTR are the BGR/ABGR formats (as > listed in the 'AFBC formats' table) > > Thus, any other permutation of the components might make it incompatible > with some other AFBC producers/consumers. Uh, that's not how this is supposed to be used. Drivers are meant to expose _everything_ they support (bonus if you roughly sort it in preference order). Userspace then computes the intersection of modifiers/formats supported by all devices it needs to share a buffer with. Allowing that was the entire point of modifiers, if we artificially limit to the common denominator we're back "only linear works everywhere". -Daniel > > > > > But why if the HW (GPU and DPU) is capable of ? > > > > Isn't it an userspace choice ? I understand XRGB8888 is a waste > > of memory space and compression efficiency, but this is not the > > kernel driver's to decide this, right ? > It is a reccomendation by the AFBC spec. As far as I understand, it > depends upon the implementor of the AFBC spec(ie dpu, gpu, vpu, etc) > to allow/disallow *X* formats for AFBC encoding/decoding. > > > > > For interoperability I'll understand recommending a minimal set > > of modifiers and formats. But here, each platform is also limited > > by it's GPU capabilites aswell. > Agreed > > > > > Limiting to ABGR8888 would discard like every non-Android renderers, > > using AFBC, I'm not sure it's the kernels driver's responsibility. > I am not familiar with non-Android renderers. > > > > > > > > Thus, DRM_FORMAT_ABGR, DRM_FORMAT_BGR should only be allowed. > > >> + line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7; > > >> + break; > > >> + } > > >> + > > >> + return ((line_stride + 1) >> 1) << 1; > > >> +} > > >> + > > >> static void meson_plane_atomic_update(struct drm_plane *plane, > > >> struct drm_plane_state *old_state) > > >> { > > > > [...] > > > > >> > > >> +static bool meson_plane_format_mod_supported(struct drm_plane *plane, > > >> + u32 format, u64 modifier) > > >> +{ > > >> + struct meson_plane *meson_plane = to_meson_plane(plane); > > >> + struct meson_drm *priv = meson_plane->priv; > > >> + int i; > > >> + > > >> + if (modifier == DRM_FORMAT_MOD_INVALID) > > >> + return false; > > >> + > > >> + if (modifier == DRM_FORMAT_MOD_LINEAR) > > >> + return true; > > >> + > > >> + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) && > > >> + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > > >> + return false; > > >> + > > >> + if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) > > >> + return false; > > >> + > > >> + for (i = 0 ; i < plane->modifier_count ; ++i) > > >> + if (plane->modifiers[i] == modifier) > > >> + break; > > >> + > > >> + if (i == plane->modifier_count) { > > >> + DRM_DEBUG_KMS("Unsupported modifier\n"); > > >> + return false; > > >> + } > > > > I can add a warn_once here, would it be enough ? > > > > >> + > > >> + if (priv->afbcd.ops && priv->afbcd.ops->supported_fmt) > > >> + return priv->afbcd.ops->supported_fmt(modifier, format); > > >> + > > >> + DRM_DEBUG_KMS("AFBC Unsupported\n"); > > >> + return false; > > >> +} > > >> + > > >> static const struct drm_plane_funcs meson_plane_funcs = { > > >> .update_plane = drm_atomic_helper_update_plane, > > >> .disable_plane = drm_atomic_helper_disable_plane, > > >> @@ -353,6 +457,7 @@ static const struct drm_plane_funcs meson_plane_funcs = { > > >> .reset = drm_atomic_helper_plane_reset, > > >> .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, > > >> .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, > > >> + .format_mod_supported = meson_plane_format_mod_supported, > > >> }; > > >> > > >> static const uint32_t supported_drm_formats[] = { > > >> @@ -364,10 +469,53 @@ static const uint32_t supported_drm_formats[] = { > > >> DRM_FORMAT_RGB565, > > >> }; > > >> > > >> +static const uint64_t format_modifiers_afbc_gxm[] = { > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_YTR), > > >> + /* SPLIT mandates SPARSE, RGB modes mandates YTR */ > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_SPLIT), > > >> + DRM_FORMAT_MOD_LINEAR, > > >> + DRM_FORMAT_MOD_INVALID, > > >> +}; > > >> + > > >> +static const uint64_t format_modifiers_afbc_g12a[] = { > > >> + /* > > >> + * - TOFIX Support AFBC modifiers for YUV formats (16x16 + TILED) > > >> + * - AFBC_FORMAT_MOD_YTR is mandatory since we only support RGB > > >> + * - SPLIT is mandatory for performances reasons when in 16x16 > > >> + * block size > > >> + * - 32x8 block size + SPLIT is mandatory with 4K frame size > > >> + * for performances reasons > > >> + */ > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_SPLIT), > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE), > > >> + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > > >> + AFBC_FORMAT_MOD_YTR | > > >> + AFBC_FORMAT_MOD_SPARSE | > > >> + AFBC_FORMAT_MOD_SPLIT), > > >> + DRM_FORMAT_MOD_LINEAR, > > >> + DRM_FORMAT_MOD_INVALID, > > >> +}; > > >> + > > >> +static const uint64_t format_modifiers_default[] = { > > >> + DRM_FORMAT_MOD_LINEAR, > > >> + DRM_FORMAT_MOD_INVALID, > > >> +}; > > >> + > > >> int meson_plane_create(struct meson_drm *priv) > > >> { > > >> struct meson_plane *meson_plane; > > >> struct drm_plane *plane; > > >> + const uint64_t *format_modifiers = format_modifiers_default; > > >> > > >> meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), > > >> GFP_KERNEL); > > >> @@ -377,11 +525,16 @@ int meson_plane_create(struct meson_drm *priv) > > >> meson_plane->priv = priv; > > >> plane = &meson_plane->base; > > >> > > >> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) > > >> + format_modifiers = format_modifiers_afbc_gxm; > > >> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > > >> + format_modifiers = format_modifiers_afbc_g12a; > > >> + > > >> drm_universal_plane_init(priv->drm, plane, 0xFF, > > >> &meson_plane_funcs, > > >> supported_drm_formats, > > >> ARRAY_SIZE(supported_drm_formats), > > >> - NULL, > > >> + format_modifiers, > > >> DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); > > >> > > >> drm_plane_helper_add(plane, &meson_plane_helper_funcs); > > >> -- > > >> 2.22.0 > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic