From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754248AbeDZJjN (ORCPT ); Thu, 26 Apr 2018 05:39:13 -0400 Received: from mail-io0-f175.google.com ([209.85.223.175]:37274 "EHLO mail-io0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753403AbeDZJjK (ORCPT ); Thu, 26 Apr 2018 05:39:10 -0400 X-Google-Smtp-Source: AB8JxZoNqq9QDEUimW5HCLoWfze0bCb+ZlhGSFOWHEilLNCqPutaslIhb2h7Mr0I+5LtquBHbzyW6oiasDqKLfb/pVM= MIME-Version: 1.0 X-Originating-IP: [2a02:168:5635:0:39d2:f87e:2033:9f6] In-Reply-To: <20180426092422.GA26825@infradead.org> References: <20180425054855.GA17038@infradead.org> <20180425064335.GB28100@infradead.org> <20180425074151.GA2271@ulmo> <20180425085439.GA29996@infradead.org> <20180425100429.GR25142@phenom.ffwll.local> <20180425153312.GD27076@infradead.org> <20180425225443.GQ16141@n2100.armlinux.org.uk> <20180426092422.GA26825@infradead.org> From: Daniel Vetter Date: Thu, 26 Apr 2018 11:39:09 +0200 Message-ID: Subject: Re: [Linaro-mm-sig] noveau vs arm dma ops To: Christoph Hellwig Cc: Russell King - ARM Linux , Linux Kernel Mailing List , amd-gfx list , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Jerome Glisse , iommu@lists.linux-foundation.org, dri-devel , Dan Williams , Thierry Reding , Logan Gunthorpe , =?UTF-8?Q?Christian_K=C3=B6nig?= , Linux ARM , "open list:DMA BUFFER SHARING FRAMEWORK" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 26, 2018 at 11:24 AM, Christoph Hellwig wrote: > On Thu, Apr 26, 2018 at 11:20:44AM +0200, Daniel Vetter wrote: >> The above is already what we're implementing in i915, at least >> conceptually (it all boils down to clflush instructions because those >> both invalidate and flush). > > The clwb instruction that just writes back dirty cache lines might > be very interesting for the x86 non-coherent dma case. A lot of > architectures use their equivalent to prepare to to device transfers. Iirc didn't help for i915 use-cases much. Either data gets streamed between cpu and gpu, and then keeping the clean cacheline around doesn't buy you anything. In other cases we need to flush because the gpu really wants to use non-snooped transactions (faster/lower latency/less power required for display because you can shut down the caches), and then there's also no benefit with keeping the cacheline around (no one will ever need it again). I think clwb is more for persistent memory and stuff like that, not so much for gpus. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [Linaro-mm-sig] noveau vs arm dma ops Date: Thu, 26 Apr 2018 11:39:09 +0200 Message-ID: References: <20180425054855.GA17038@infradead.org> <20180425064335.GB28100@infradead.org> <20180425074151.GA2271@ulmo> <20180425085439.GA29996@infradead.org> <20180425100429.GR25142@phenom.ffwll.local> <20180425153312.GD27076@infradead.org> <20180425225443.GQ16141@n2100.armlinux.org.uk> <20180426092422.GA26825@infradead.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180426092422.GA26825@infradead.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Christoph Hellwig Cc: Linux Kernel Mailing List , iommu@lists.linux-foundation.org, amd-gfx list , Russell King - ARM Linux , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Jerome Glisse , dri-devel , Dan Williams , Thierry Reding , Logan Gunthorpe , =?UTF-8?Q?Christian_K=C3=B6nig?= , Linux ARM , "open list:DMA BUFFER SHARING FRAMEWORK" List-Id: iommu@lists.linux-foundation.org T24gVGh1LCBBcHIgMjYsIDIwMTggYXQgMTE6MjQgQU0sIENocmlzdG9waCBIZWxsd2lnIDxoY2hA aW5mcmFkZWFkLm9yZz4gd3JvdGU6Cj4gT24gVGh1LCBBcHIgMjYsIDIwMTggYXQgMTE6MjA6NDRB TSArMDIwMCwgRGFuaWVsIFZldHRlciB3cm90ZToKPj4gVGhlIGFib3ZlIGlzIGFscmVhZHkgd2hh dCB3ZSdyZSBpbXBsZW1lbnRpbmcgaW4gaTkxNSwgYXQgbGVhc3QKPj4gY29uY2VwdHVhbGx5IChp dCBhbGwgYm9pbHMgZG93biB0byBjbGZsdXNoIGluc3RydWN0aW9ucyBiZWNhdXNlIHRob3NlCj4+ IGJvdGggaW52YWxpZGF0ZSBhbmQgZmx1c2gpLgo+Cj4gVGhlIGNsd2IgaW5zdHJ1Y3Rpb24gdGhh dCBqdXN0IHdyaXRlcyBiYWNrIGRpcnR5IGNhY2hlIGxpbmVzIG1pZ2h0Cj4gYmUgdmVyeSBpbnRl cmVzdGluZyBmb3IgdGhlIHg4NiBub24tY29oZXJlbnQgZG1hIGNhc2UuICBBIGxvdCBvZgo+IGFy Y2hpdGVjdHVyZXMgdXNlIHRoZWlyIGVxdWl2YWxlbnQgdG8gcHJlcGFyZSB0byB0byBkZXZpY2Ug dHJhbnNmZXJzLgoKSWlyYyBkaWRuJ3QgaGVscCBmb3IgaTkxNSB1c2UtY2FzZXMgbXVjaC4gRWl0 aGVyIGRhdGEgZ2V0cyBzdHJlYW1lZApiZXR3ZWVuIGNwdSBhbmQgZ3B1LCBhbmQgdGhlbiBrZWVw aW5nIHRoZSBjbGVhbiBjYWNoZWxpbmUgYXJvdW5kCmRvZXNuJ3QgYnV5IHlvdSBhbnl0aGluZy4g SW4gb3RoZXIgY2FzZXMgd2UgbmVlZCB0byBmbHVzaCBiZWNhdXNlIHRoZQpncHUgcmVhbGx5IHdh bnRzIHRvIHVzZSBub24tc25vb3BlZCB0cmFuc2FjdGlvbnMgKGZhc3Rlci9sb3dlcgpsYXRlbmN5 L2xlc3MgcG93ZXIgcmVxdWlyZWQgZm9yIGRpc3BsYXkgYmVjYXVzZSB5b3UgY2FuIHNodXQgZG93 biB0aGUKY2FjaGVzKSwgYW5kIHRoZW4gdGhlcmUncyBhbHNvIG5vIGJlbmVmaXQgd2l0aCBrZWVw aW5nIHRoZSBjYWNoZWxpbmUKYXJvdW5kIChubyBvbmUgd2lsbCBldmVyIG5lZWQgaXQgYWdhaW4p LgoKSSB0aGluayBjbHdiIGlzIG1vcmUgZm9yIHBlcnNpc3RlbnQgbWVtb3J5IGFuZCBzdHVmZiBs aWtlIHRoYXQsIG5vdCBzbwptdWNoIGZvciBncHVzLgotRGFuaWVsCi0tIApEYW5pZWwgVmV0dGVy ClNvZnR3YXJlIEVuZ2luZWVyLCBJbnRlbCBDb3Jwb3JhdGlvbgorNDEgKDApIDc5IDM2NSA1NyA0 OCAtIGh0dHA6Ly9ibG9nLmZmd2xsLmNoCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZy ZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3Rp bmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: daniel.vetter@ffwll.ch (Daniel Vetter) Date: Thu, 26 Apr 2018 11:39:09 +0200 Subject: [Linaro-mm-sig] noveau vs arm dma ops In-Reply-To: <20180426092422.GA26825@infradead.org> References: <20180425054855.GA17038@infradead.org> <20180425064335.GB28100@infradead.org> <20180425074151.GA2271@ulmo> <20180425085439.GA29996@infradead.org> <20180425100429.GR25142@phenom.ffwll.local> <20180425153312.GD27076@infradead.org> <20180425225443.GQ16141@n2100.armlinux.org.uk> <20180426092422.GA26825@infradead.org> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Apr 26, 2018 at 11:24 AM, Christoph Hellwig wrote: > On Thu, Apr 26, 2018 at 11:20:44AM +0200, Daniel Vetter wrote: >> The above is already what we're implementing in i915, at least >> conceptually (it all boils down to clflush instructions because those >> both invalidate and flush). > > The clwb instruction that just writes back dirty cache lines might > be very interesting for the x86 non-coherent dma case. A lot of > architectures use their equivalent to prepare to to device transfers. Iirc didn't help for i915 use-cases much. Either data gets streamed between cpu and gpu, and then keeping the clean cacheline around doesn't buy you anything. In other cases we need to flush because the gpu really wants to use non-snooped transactions (faster/lower latency/less power required for display because you can shut down the caches), and then there's also no benefit with keeping the cacheline around (no one will ever need it again). I think clwb is more for persistent memory and stuff like that, not so much for gpus. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch