From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757625AbaGWJaq (ORCPT ); Wed, 23 Jul 2014 05:30:46 -0400 Received: from mail-ie0-f175.google.com ([209.85.223.175]:43733 "EHLO mail-ie0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757233AbaGWJao convert rfc822-to-8bit (ORCPT ); Wed, 23 Jul 2014 05:30:44 -0400 MIME-Version: 1.0 X-Originating-IP: [84.73.67.144] In-Reply-To: <53CF8010.9060809@amd.com> References: <20140709093124.11354.3774.stgit@patser> <20140722115737.GN15237@phenom.ffwll.local> <53CE56ED.4040109@vodafone.de> <20140722132652.GO15237@phenom.ffwll.local> <53CE6AFA.1060807@vodafone.de> <53CE84AA.9030703@amd.com> <53CE8A57.2000803@vodafone.de> <53CF58FB.8070609@canonical.com> <53CF5B9F.1050800@amd.com> <53CF5EFE.6070307@canonical.com> <53CF63C2.7070407@vodafone.de> <53CF6622.6060803@amd.com> <53CF699D.9070902@canonical.com> <53CF6B18.5070107@vodafone.de> <53CF7035.2060808@amd.com> <53CF7191.2090008@canonical.com> <53CF765E.7020802@vodafone.de> <53CF8010.9060809@amd.com> Date: Wed, 23 Jul 2014 11:30:44 +0200 Message-ID: Subject: Re: [Nouveau] [PATCH 09/17] drm/radeon: use common fence implementation for fences From: Daniel Vetter To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: =?UTF-8?Q?Christian_K=C3=B6nig?= , Maarten Lankhorst , Thomas Hellstrom , nouveau , LKML , dri-devel , Ben Skeggs , "Deucher, Alexander" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 23, 2014 at 11:27 AM, Christian König wrote: > You submit a job to the hardware and then block the job to wait for radeon > to be finished? Well than this would indeed require a hardware reset, but > wouldn't that make the whole problem even worse? > > I mean currently we block one userspace process to wait for other hardware > to be finished with a buffer, but what you are describing here blocks the > whole hardware to wait for other hardware which in the end blocks all > userspace process accessing the hardware. There is nothing new here with prime - if one context hangs the gpu it blocks everyone else on i915. > Talking about alternative approaches wouldn't it be simpler to just offload > the waiting to a different kernel or userspace thread? Well this is exactly what we'll do once we have the scheduler. But this is an orthogonal issue imo. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 09/17] drm/radeon: use common fence implementation for fences Date: Wed, 23 Jul 2014 11:30:44 +0200 Message-ID: References: <20140709093124.11354.3774.stgit@patser> <20140722115737.GN15237@phenom.ffwll.local> <53CE56ED.4040109@vodafone.de> <20140722132652.GO15237@phenom.ffwll.local> <53CE6AFA.1060807@vodafone.de> <53CE84AA.9030703@amd.com> <53CE8A57.2000803@vodafone.de> <53CF58FB.8070609@canonical.com> <53CF5B9F.1050800@amd.com> <53CF5EFE.6070307@canonical.com> <53CF63C2.7070407@vodafone.de> <53CF6622.6060803@amd.com> <53CF699D.9070902@canonical.com> <53CF6B18.5070107@vodafone.de> <53CF7035.2060808@amd.com> <53CF7191.2090008@canonical.com> <53CF765E.7020802@vodafone.de> <53CF8010.9060809@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <53CF8010.9060809-5C7GfCeVMHo@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: Thomas Hellstrom , nouveau , LKML , dri-devel , "Deucher, Alexander" , =?UTF-8?Q?Christian_K=C3=B6nig?= , Ben Skeggs List-Id: nouveau.vger.kernel.org T24gV2VkLCBKdWwgMjMsIDIwMTQgYXQgMTE6MjcgQU0sIENocmlzdGlhbiBLw7ZuaWcKPGNocmlz dGlhbi5rb2VuaWdAYW1kLmNvbT4gd3JvdGU6Cj4gWW91IHN1Ym1pdCBhIGpvYiB0byB0aGUgaGFy ZHdhcmUgYW5kIHRoZW4gYmxvY2sgdGhlIGpvYiB0byB3YWl0IGZvciByYWRlb24KPiB0byBiZSBm aW5pc2hlZD8gV2VsbCB0aGFuIHRoaXMgd291bGQgaW5kZWVkIHJlcXVpcmUgYSBoYXJkd2FyZSBy ZXNldCwgYnV0Cj4gd291bGRuJ3QgdGhhdCBtYWtlIHRoZSB3aG9sZSBwcm9ibGVtIGV2ZW4gd29y c2U/Cj4KPiBJIG1lYW4gY3VycmVudGx5IHdlIGJsb2NrIG9uZSB1c2Vyc3BhY2UgcHJvY2VzcyB0 byB3YWl0IGZvciBvdGhlciBoYXJkd2FyZQo+IHRvIGJlIGZpbmlzaGVkIHdpdGggYSBidWZmZXIs IGJ1dCB3aGF0IHlvdSBhcmUgZGVzY3JpYmluZyBoZXJlIGJsb2NrcyB0aGUKPiB3aG9sZSBoYXJk d2FyZSB0byB3YWl0IGZvciBvdGhlciBoYXJkd2FyZSB3aGljaCBpbiB0aGUgZW5kIGJsb2NrcyBh bGwKPiB1c2Vyc3BhY2UgcHJvY2VzcyBhY2Nlc3NpbmcgdGhlIGhhcmR3YXJlLgoKVGhlcmUgaXMg bm90aGluZyBuZXcgaGVyZSB3aXRoIHByaW1lIC0gaWYgb25lIGNvbnRleHQgaGFuZ3MgdGhlIGdw dSBpdApibG9ja3MgZXZlcnlvbmUgZWxzZSBvbiBpOTE1LgoKPiBUYWxraW5nIGFib3V0IGFsdGVy bmF0aXZlIGFwcHJvYWNoZXMgd291bGRuJ3QgaXQgYmUgc2ltcGxlciB0byBqdXN0IG9mZmxvYWQK PiB0aGUgd2FpdGluZyB0byBhIGRpZmZlcmVudCBrZXJuZWwgb3IgdXNlcnNwYWNlIHRocmVhZD8K CldlbGwgdGhpcyBpcyBleGFjdGx5IHdoYXQgd2UnbGwgZG8gb25jZSB3ZSBoYXZlIHRoZSBzY2hl ZHVsZXIuIEJ1dAp0aGlzIGlzIGFuIG9ydGhvZ29uYWwgaXNzdWUgaW1vLgotRGFuaWVsCi0tIApE YW5pZWwgVmV0dGVyClNvZnR3YXJlIEVuZ2luZWVyLCBJbnRlbCBDb3Jwb3JhdGlvbgorNDEgKDAp IDc5IDM2NSA1NyA0OCAtIGh0dHA6Ly9ibG9nLmZmd2xsLmNoCl9fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fCk5vdXZlYXUgbWFpbGluZyBsaXN0Ck5vdXZlYXVA bGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1h bi9saXN0aW5mby9ub3V2ZWF1Cg==