From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 2/4] drm/i915: merge VLV eDP and DP AUX
 clock divider calculation
Date: Tue, 21 May 2013 12:42:30 +0200
Message-ID: <CAKMK7uFWL3AUq8na4qBJ0GKGfvXBDwuV4Dga2OePPgX-a+erOw@mail.gmail.com>
References: <1368704437-17034-1-git-send-email-imre.deak@intel.com>
	<1368704437-17034-3-git-send-email-imre.deak@intel.com>
	<20130521091201.GG12292@phenom.ffwll.local>
	<1369132599.15652.32.camel@intelbox>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com
	[209.85.223.180])
	by gabe.freedesktop.org (Postfix) with ESMTP id 19D87E5C52
	for <intel-gfx@lists.freedesktop.org>;
	Tue, 21 May 2013 03:42:30 -0700 (PDT)
Received: by mail-ie0-f180.google.com with SMTP id ar20so961045iec.25
	for <intel-gfx@lists.freedesktop.org>;
	Tue, 21 May 2013 03:42:30 -0700 (PDT)
In-Reply-To: <1369132599.15652.32.camel@intelbox>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Tue, May 21, 2013 at 12:36 PM, Imre Deak <imre.deak@intel.com> wrote:
> On Tue, 2013-05-21 at 11:12 +0200, Daniel Vetter wrote:
>> On Thu, May 16, 2013 at 02:40:35PM +0300, Imre Deak wrote:
>> > On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we
>> > can calculate for both the clock divider for the 2MHz target rate at the
>> > same place. Afterwards we can also replace the is_cpu_edp() check with a
>> > check for port A.
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>>
>> There's a now-dead IS_VLV case in intel_hrawclk which should be killed
>> with this patch, too.
>
> Shouldn't it still return the correct value if someone calls it in the
> future? Actually it's also used in
> intel_dp_init_panel_power_sequencer_registers().

Indeed. I think though it's better to make this an explicit vlv case
since hrawclk talks about the FSB. And that thing pretty surely
doesn't exist on vlv any more ;-) So maybe a follow-up patch?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch