From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26DFEC48BE5 for ; Wed, 23 Jun 2021 14:51:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E569060041 for ; Wed, 23 Jun 2021 14:51:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E569060041 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 34BD96E926; Wed, 23 Jun 2021 14:51:00 +0000 (UTC) Received: from mail-ot1-x335.google.com (mail-ot1-x335.google.com [IPv6:2607:f8b0:4864:20::335]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FB896E921 for ; Wed, 23 Jun 2021 14:50:58 +0000 (UTC) Received: by mail-ot1-x335.google.com with SMTP id n99-20020a9d206c0000b029045d4f996e62so2190082ota.4 for ; Wed, 23 Jun 2021 07:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=mLK+t9vbBMf5eQK1453iefhEKkMWDs/+WdTBxGANbmU=; b=DQ4I6rKH4Sb7nUJ1kDBPVglIYR9klQ6uzr24M5E+IML8qk1fk8PczQU/yk60BWD4RD jc/ugGtks5sVbhFzbK+qS+3RFnPO+w5zOQ0HqMgapPsSnjPHZv+4IpMlxSiVoNpjwvNN oyaZwWHNS1/Zm2hgSLeoY8eYCuHwjqPJO0y3Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=mLK+t9vbBMf5eQK1453iefhEKkMWDs/+WdTBxGANbmU=; b=LZv6b+bAoH2vAC5lu/lHA7JFRXorYF1oQwoBQboQdrXquZKOzR1aytUMzDsGAZTUTU Umud/vTGDkAaVUvmszmjDZv8Y32guZfgdl6Z3mkFbGsb0KnB9nB4NJEMjy2lRaI8+GMP aUqca+HFsfA6qWnQzr3cqakLnMfBC7LxT68Skq+eWMrtPqmmxSVhKZa6AjBbFQIBg7Pg N0NE5hgaRPEqCDQWMclNMco4oleOYsQ3jGCeaHec1vQVdMzRyIQLJQAxmiLAbClgr0pn cPbjp7QyOKhCP5sFu801gECzFrpdxxxGPyiOalOQjF8o6Z++ekRSyh5B/NLDyWC3QPZb RXNA== X-Gm-Message-State: AOAM533cUlEI16aXVbsyUXpvRvDawqGnXr/6FBb6Bd4opZT0URpI6zjA v8zZ8ylanPNmZY8ux2tlg82jZ4NyJADDziT6C59x1Q== X-Google-Smtp-Source: ABdhPJwepdGBrzdDtB8NbnIjNfZukLgkURi/E6/D407xWoqeY1N/4o1WVrchBWB0lb87samOU9kH5E7Xa/sycejkvVU= X-Received: by 2002:a05:6830:2370:: with SMTP id r16mr261588oth.188.1624459857447; Wed, 23 Jun 2021 07:50:57 -0700 (PDT) MIME-Version: 1.0 References: <20210622165511.3169559-1-daniel.vetter@ffwll.ch> <20210622165511.3169559-16-daniel.vetter@ffwll.ch> <3bf45006-4256-763d-601b-3a25a7057820@amd.com> <421cb10d-92a7-0780-3d38-d4cabd008c0c@amd.com> <682d2f3b-8ba3-cccb-1385-1f74f0b06ada@amd.com> In-Reply-To: <682d2f3b-8ba3-cccb-1385-1f74f0b06ada@amd.com> From: Daniel Vetter Date: Wed, 23 Jun 2021 16:50:46 +0200 Message-ID: Subject: Re: [PATCH 15/15] RFC: drm/amdgpu: Implement a proper implicit fencing uapi To: =?UTF-8?Q?Christian_K=C3=B6nig?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Daniel Stone , Daniel Vetter , Intel Graphics Development , Kevin Wang , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Luben Tuikov , "Kristian H . Kristensen" , Chen Li , Alex Deucher , mesa-dev , =?UTF-8?Q?Michel_D=C3=A4nzer?= , Dennis Li , Deepak R Varma Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Jun 23, 2021 at 4:02 PM Christian K=C3=B6nig wrote: > > Am 23.06.21 um 15:49 schrieb Daniel Vetter: > > On Wed, Jun 23, 2021 at 3:44 PM Christian K=C3=B6nig > > wrote: > >> Am 23.06.21 um 15:38 schrieb Bas Nieuwenhuizen: > >>> On Wed, Jun 23, 2021 at 2:59 PM Christian K=C3=B6nig > >>> wrote: > >>>> Am 23.06.21 um 14:18 schrieb Daniel Vetter: > >>>>> On Wed, Jun 23, 2021 at 11:45 AM Bas Nieuwenhuizen > >>>>> wrote: > >>>>>> On Tue, Jun 22, 2021 at 6:55 PM Daniel Vetter wrote: > >>>>>>> WARNING: Absolutely untested beyond "gcc isn't dying in agony". > >>>>>>> > >>>>>>> Implicit fencing done properly needs to treat the implicit fencin= g > >>>>>>> slots like a funny kind of IPC mailbox. In other words it needs t= o be > >>>>>>> explicitly. This is the only way it will mesh well with explicit > >>>>>>> fencing userspace like vk, and it's also the bare minimum require= d to > >>>>>>> be able to manage anything else that wants to use the same buffer= on > >>>>>>> multiple engines in parallel, and still be able to share it throu= gh > >>>>>>> implicit sync. > >>>>>>> > >>>>>>> amdgpu completely lacks such an uapi. Fix this. > >>>>>>> > >>>>>>> Luckily the concept of ignoring implicit fences exists already, a= nd > >>>>>>> takes care of all the complexities of making sure that non-option= al > >>>>>>> fences (like bo moves) are not ignored. This support was added in > >>>>>>> > >>>>>>> commit 177ae09b5d699a5ebd1cafcee78889db968abf54 > >>>>>>> Author: Andres Rodriguez > >>>>>>> Date: Fri Sep 15 20:44:06 2017 -0400 > >>>>>>> > >>>>>>> drm/amdgpu: introduce AMDGPU_GEM_CREATE_EXPLICIT_SYNC v2 > >>>>>>> > >>>>>>> Unfortuantely it's the wrong semantics, because it's a bo flag an= d > >>>>>>> disables implicit sync on an allocated buffer completely. > >>>>>>> > >>>>>>> We _do_ want implicit sync, but control it explicitly. For this w= e > >>>>>>> need a flag on the drm_file, so that a given userspace (like vulk= an) > >>>>>>> can manage the implicit sync slots explicitly. The other side of = the > >>>>>>> pipeline (compositor, other process or just different stage in a = media > >>>>>>> pipeline in the same process) can then either do the same, or ful= ly > >>>>>>> participate in the implicit sync as implemented by the kernel by > >>>>>>> default. > >>>>>>> > >>>>>>> By building on the existing flag for buffers we avoid any issues = with > >>>>>>> opening up additional security concerns - anything this new flag = here > >>>>>>> allows is already. > >>>>>>> > >>>>>>> All drivers which supports this concept of a userspace-specific > >>>>>>> opt-out of implicit sync have a flag in their CS ioctl, but in re= ality > >>>>>>> that turned out to be a bit too inflexible. See the discussion be= low, > >>>>>>> let's try to do a bit better for amdgpu. > >>>>>>> > >>>>>>> This alone only allows us to completely avoid any stalls due to > >>>>>>> implicit sync, it does not yet allow us to use implicit sync as a > >>>>>>> strange form of IPC for sync_file. > >>>>>>> > >>>>>>> For that we need two more pieces: > >>>>>>> > >>>>>>> - a way to get the current implicit sync fences out of a buffer. = Could > >>>>>>> be done in a driver ioctl, but everyone needs this, and gene= rally a > >>>>>>> dma-buf is involved anyway to establish the sharing. So an i= octl on > >>>>>>> the dma-buf makes a ton more sense: > >>>>>>> > >>>>>>> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%= 3A%2F%2Flore.kernel.org%2Fdri-devel%2F20210520190007.534046-4-jason%40jleks= trand.net%2F&data=3D04%7C01%7Cchristian.koenig%40amd.com%7C83dbdd0a1eb8= 442cbf7108d9364db51e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637600529= 684040802%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT= iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3DfbdwtutEj93anZp6Pshs277QoMTHZx= Iy0Yl54T95rCw%3D&reserved=3D0 > >>>>>>> > >>>>>>> Current drivers in upstream solves this by having the opt-ou= t flag > >>>>>>> on their CS ioctl. This has the downside that very often the= CS > >>>>>>> which must actually stall for the implicit fence is run a wh= ile > >>>>>>> after the implicit fence point was logically sampled per the= api > >>>>>>> spec (vk passes an explicit syncobj around for that afaiui),= and so > >>>>>>> results in oversync. Converting the implicit sync fences int= o a > >>>>>>> snap-shot sync_file is actually accurate. > >>>>>>> > >>>>>>> - Simillar we need to be able to set the exclusive implicit fence= . > >>>>>>> Current drivers again do this with a CS ioctl flag, with aga= in the > >>>>>>> same problems that the time the CS happens additional depend= encies > >>>>>>> have been added. An explicit ioctl to only insert a sync_fil= e (while > >>>>>>> respecting the rules for how exclusive and shared fence slot= s must > >>>>>>> be update in struct dma_resv) is much better. This is propos= ed here: > >>>>>>> > >>>>>>> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%= 3A%2F%2Flore.kernel.org%2Fdri-devel%2F20210520190007.534046-5-jason%40jleks= trand.net%2F&data=3D04%7C01%7Cchristian.koenig%40amd.com%7C83dbdd0a1eb8= 442cbf7108d9364db51e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637600529= 684040802%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT= iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3Dvv%2BREnWorjoTOwrD1jH1GHVQcjPy= 1oesaophsz056aI%3D&reserved=3D0 > >>>>>>> > >>>>>>> These three pieces together allow userspace to fully control impl= icit > >>>>>>> fencing and remove all unecessary stall points due to them. > >>>>>>> > >>>>>>> Well, as much as the implicit fencing model fundamentally allows: > >>>>>>> There is only one set of fences, you can only choose to sync agai= nst > >>>>>>> only writers (exclusive slot), or everyone. Hence suballocating > >>>>>>> multiple buffers or anything else like this is fundamentally not > >>>>>>> possible, and can only be fixed by a proper explicit fencing mode= l. > >>>>>>> > >>>>>>> Aside from that caveat this model gets implicit fencing as closel= y to > >>>>>>> explicit fencing semantics as possible: > >>>>>>> > >>>>>>> On the actual implementation I opted for a simple setparam ioctl,= no > >>>>>>> locking (just atomic reads/writes) for simplicity. There is a nic= e > >>>>>>> flag parameter in the VM ioctl which we could use, except: > >>>>>>> - it's not checked, so userspace likely passes garbage > >>>>>>> - there's already a comment that userspace _does_ pass garbage in= the > >>>>>>> priority field > >>>>>>> So yeah unfortunately this flag parameter for setting vm flags is > >>>>>>> useless, and we need to hack up a new one. > >>>>>>> > >>>>>>> v2: Explain why a new SETPARAM (Jason) > >>>>>>> > >>>>>>> v3: Bas noticed I forgot to hook up the dependency-side shortcut.= We > >>>>>>> need both, or this doesn't do much. > >>>>>>> > >>>>>>> v4: Rebase over the amdgpu patch to always set the implicit sync > >>>>>>> fences. > >>>>>> So I think there is still a case missing in this implementation. > >>>>>> Consider these 3 cases > >>>>>> > >>>>>> (format: a->b: b waits on a. Yes, I know arrows are hard) > >>>>>> > >>>>>> explicit->explicit: This doesn't wait now, which is good > >>>>>> Implicit->explicit: This doesn't wait now, which is good > >>>>>> explicit->implicit : This still waits as the explicit submission s= till > >>>>>> adds shared fences and most things that set an exclusive fence for > >>>>>> implicit sync will hence wait on it. > >>>>>> > >>>>>> This is probably good enough for what radv needs now but also soun= ds > >>>>>> like a risk wrt baking in new uapi behavior that we don't want to = be > >>>>>> the end result. > >>>>>> > >>>>>> Within AMDGPU this is probably solvable in two ways: > >>>>>> > >>>>>> 1) Downgrade AMDGPU_SYNC_NE_OWNER to AMDGPU_SYNC_EXPLICIT for shar= ed fences. > >>>>> I'm not sure that works. I think the right fix is that radeonsi als= o > >>>>> switches to this model, with maybe a per-bo CS flag to set indicate > >>>>> write access, to cut down on the number of ioctls that are needed > >>>>> otherwise on shared buffers. This per-bo flag would essentially sel= ect > >>>>> between SYNC_NE_OWNER and SYNC_EXPLICIT on a per-buffer basis. > >>>> Yeah, but I'm still not entirely sure why that approach isn't suffic= ient? > >>>> > >>>> Problem with the per context or per vm flag is that you then don't g= et > >>>> any implicit synchronization any more when another process starts us= ing > >>>> the buffer. > >>> That is exactly what I want for Vulkan :) > >> Yeah, but as far as I know this is not something we can do. > >> > >> See we have use cases like screen capture and debug which rely on that > >> behavior. > > They will keep working, if (and only if) the vulkan side sets the > > winsys fences correctly. Also, everything else in vulkan aside from > > winsys is explicitly not synced at all, you have to import drm syncobj > > timeline on the gl side. > > > >> The only thing we can do is to say on a per buffer flag that a buffer > >> should not participate in implicit sync at all. > > Nah, this doesn't work. Because it's not a global decision, is a local > > decision for the rendered. Vulkan wants to control implicit sync > > explicitly, and the kernel can't force more synchronization. If a > > buffer is shared as a winsys buffer between vulkan client and gl using > > compositor, then you _have_ to use implicit sync on it. But vk needs > > to set the fences directly (and if the app gets it wrong, you get > > misrendering, but that is the specified behavour of vulkan). > > Yeah, but that's exactly what we tried to avoid. > > Mhm, when we attach the flag to the process/VM then this would break the > use case of VA-API and Vulkan in the same process. > > But I think if you attach the flag to the context that should indeed > work fine. Yeah that's a question I have, whether the drm_file is shared within one process among everything, or whether radeonsi/libva/vk each have their own. If each have their own drm_file, then we should be fine, otherwise we need to figure out another place to put this (worst case as a CS extension that vk just sets on every submit). Also yes this risks that a vk app which was violationing the winsys spec will now break, which is why I think we should do this sooner than later. Otherwise the list of w/a we might need to apply in vk userspace will become very long :-( At least since this is purely opt-in from userspace, we only need to have the w/a list in userspace, where mesa has the infrastructure for that already. -Daniel > > Christian. > > > -Daniel > > > >> Regards, > >> Christian. > >> > >>>>> The current amdgpu uapi just doesn't allow any other model without = an > >>>>> explicit opt-in. So current implicit sync userspace just has to > >>>>> oversync, there's not much choice. > >>>>> > >>>>>> 2) Have an EXPLICIT fence owner that is used for explicit submissi= ons > >>>>>> that is ignored by AMDGPU_SYNC_NE_OWNER. > >>>>>> > >>>>>> But this doesn't solve cross-driver interactions here. > >>>>> Yeah cross-driver is still entirely unsolved, because > >>>>> amdgpu_bo_explicit_sync() on the bo didn't solve that either. > >>>> Hui? You have lost me. Why is that still unsolved? > >>> The part we're trying to solve with this patch is Vulkan should not > >>> participate in any implicit sync at all wrt submissions (and then > >>> handle the implicit sync for WSI explicitly using the fence > >>> import/export stuff that Jason wrote). As long we add shared fences t= o > >>> the dma_resv we participate in implicit sync (at the level of an > >>> implicit sync read) still, at least from the perspective of later job= s > >>> waiting on these fences. > >>> > >>>> Regards, > >>>> Christian. > >>>> > >>>>> -Daniel > >>>>> > >>>>>>> Cc: mesa-dev@lists.freedesktop.org > >>>>>>> Cc: Bas Nieuwenhuizen > >>>>>>> Cc: Dave Airlie > >>>>>>> Cc: Rob Clark > >>>>>>> Cc: Kristian H. Kristensen > >>>>>>> Cc: Michel D=C3=A4nzer > >>>>>>> Cc: Daniel Stone > >>>>>>> Cc: Sumit Semwal > >>>>>>> Cc: "Christian K=C3=B6nig" > >>>>>>> Cc: Alex Deucher > >>>>>>> Cc: Daniel Vetter > >>>>>>> Cc: Deepak R Varma > >>>>>>> Cc: Chen Li > >>>>>>> Cc: Kevin Wang > >>>>>>> Cc: Dennis Li > >>>>>>> Cc: Luben Tuikov > >>>>>>> Cc: linaro-mm-sig@lists.linaro.org > >>>>>>> Signed-off-by: Daniel Vetter > >>>>>>> --- > >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +++++-- > >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 21 ++++++++++++++++= +++++ > >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 ++++++ > >>>>>>> include/uapi/drm/amdgpu_drm.h | 10 ++++++++++ > >>>>>>> 4 files changed, 42 insertions(+), 2 deletions(-) > >>>>>>> > >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu= /drm/amd/amdgpu/amdgpu_cs.c > >>>>>>> index 65df34c17264..c5386d13eb4a 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c > >>>>>>> @@ -498,6 +498,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu= _cs_parser *p, > >>>>>>> struct amdgpu_bo *gds; > >>>>>>> struct amdgpu_bo *gws; > >>>>>>> struct amdgpu_bo *oa; > >>>>>>> + bool no_implicit_sync =3D READ_ONCE(fpriv->vm.no_implicit= _sync); > >>>>>>> int r; > >>>>>>> > >>>>>>> INIT_LIST_HEAD(&p->validated); > >>>>>>> @@ -577,7 +578,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu= _cs_parser *p, > >>>>>>> > >>>>>>> e->bo_va =3D amdgpu_vm_bo_find(vm, bo); > >>>>>>> > >>>>>>> - if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_s= ync(bo)) { > >>>>>>> + if (bo->tbo.base.dma_buf && > >>>>>>> + !(no_implicit_sync || amdgpu_bo_explicit_sync= (bo))) { > >>>>>>> e->chain =3D dma_fence_chain_alloc(); > >>>>>>> if (!e->chain) { > >>>>>>> r =3D -ENOMEM; > >>>>>>> @@ -649,6 +651,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu= _cs_parser *p) > >>>>>>> { > >>>>>>> struct amdgpu_fpriv *fpriv =3D p->filp->driver_priv; > >>>>>>> struct amdgpu_bo_list_entry *e; > >>>>>>> + bool no_implicit_sync =3D READ_ONCE(fpriv->vm.no_implicit= _sync); > >>>>>>> int r; > >>>>>>> > >>>>>>> list_for_each_entry(e, &p->validated, tv.head) { > >>>>>>> @@ -656,7 +659,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu= _cs_parser *p) > >>>>>>> struct dma_resv *resv =3D bo->tbo.base.resv; > >>>>>>> enum amdgpu_sync_mode sync_mode; > >>>>>>> > >>>>>>> - sync_mode =3D amdgpu_bo_explicit_sync(bo) ? > >>>>>>> + sync_mode =3D no_implicit_sync || amdgpu_bo_expli= cit_sync(bo) ? > >>>>>>> AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_= OWNER; > >>>>>>> r =3D amdgpu_sync_resv(p->adev, &p->job->sync,= resv, sync_mode, > >>>>>>> &fpriv->vm); > >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gp= u/drm/amd/amdgpu/amdgpu_drv.c > >>>>>>> index c080ba15ae77..f982626b5328 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > >>>>>>> @@ -1724,6 +1724,26 @@ int amdgpu_file_to_fpriv(struct file *filp= , struct amdgpu_fpriv **fpriv) > >>>>>>> return 0; > >>>>>>> } > >>>>>>> > >>>>>>> +int amdgpu_setparam_ioctl(struct drm_device *dev, void *data, > >>>>>>> + struct drm_file *filp) > >>>>>>> +{ > >>>>>>> + struct drm_amdgpu_setparam *setparam =3D data; > >>>>>>> + struct amdgpu_fpriv *fpriv =3D filp->driver_priv; > >>>>>>> + > >>>>>>> + switch (setparam->param) { > >>>>>>> + case AMDGPU_SETPARAM_NO_IMPLICIT_SYNC: > >>>>>>> + if (setparam->value) > >>>>>>> + WRITE_ONCE(fpriv->vm.no_implicit_sync, tr= ue); > >>>>>>> + else > >>>>>>> + WRITE_ONCE(fpriv->vm.no_implicit_sync, fa= lse); > >>>>>>> + break; > >>>>>>> + default: > >>>>>>> + return -EINVAL; > >>>>>>> + } > >>>>>>> + > >>>>>>> + return 0; > >>>>>>> +} > >>>>>>> + > >>>>>>> const struct drm_ioctl_desc amdgpu_ioctls_kms[] =3D { > >>>>>>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create= _ioctl, DRM_AUTH|DRM_RENDER_ALLOW), > >>>>>>> DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AU= TH|DRM_RENDER_ALLOW), > >>>>>>> @@ -1742,6 +1762,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_k= ms[] =3D { > >>>>>>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, = DRM_AUTH|DRM_RENDER_ALLOW), > >>>>>>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, = DRM_AUTH|DRM_RENDER_ALLOW), > >>>>>>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userp= tr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), > >>>>>>> + DRM_IOCTL_DEF_DRV(AMDGPU_SETPARAM, amdgpu_setparam_ioctl,= DRM_AUTH|DRM_RENDER_ALLOW), > >>>>>>> }; > >>>>>>> > >>>>>>> static const struct drm_driver amdgpu_kms_driver =3D { > >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu= /drm/amd/amdgpu/amdgpu_vm.h > >>>>>>> index ddb85a85cbba..0e8c440c6303 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > >>>>>>> @@ -321,6 +321,12 @@ struct amdgpu_vm { > >>>>>>> bool bulk_moveable; > >>>>>>> /* Flag to indicate if VM is used for compute */ > >>>>>>> bool is_compute_context; > >>>>>>> + /* > >>>>>>> + * Flag to indicate whether implicit sync should always b= e skipped on > >>>>>>> + * this context. We do not care about races at all, users= pace is allowed > >>>>>>> + * to shoot itself with implicit sync to its fullest liki= ng. > >>>>>>> + */ > >>>>>>> + bool no_implicit_sync; > >>>>>>> }; > >>>>>>> > >>>>>>> struct amdgpu_vm_manager { > >>>>>>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amd= gpu_drm.h > >>>>>>> index 0cbd1540aeac..9eae245c14d6 100644 > >>>>>>> --- a/include/uapi/drm/amdgpu_drm.h > >>>>>>> +++ b/include/uapi/drm/amdgpu_drm.h > >>>>>>> @@ -54,6 +54,7 @@ extern "C" { > >>>>>>> #define DRM_AMDGPU_VM 0x13 > >>>>>>> #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 > >>>>>>> #define DRM_AMDGPU_SCHED 0x15 > >>>>>>> +#define DRM_AMDGPU_SETPARAM 0x16 > >>>>>>> > >>>>>>> #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_B= ASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) > >>>>>>> #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_B= ASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) > >>>>>>> @@ -71,6 +72,7 @@ extern "C" { > >>>>>>> #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_B= ASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) > >>>>>>> #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND= _BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) > >>>>>>> #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BA= SE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) > >>>>>>> +#define DRM_IOCTL_AMDGPU_SETPARAM DRM_IOW(DRM_COMMAND_BASE = + DRM_AMDGPU_SETPARAM, struct drm_amdgpu_setparam) > >>>>>>> > >>>>>>> /** > >>>>>>> * DOC: memory domains > >>>>>>> @@ -306,6 +308,14 @@ union drm_amdgpu_sched { > >>>>>>> struct drm_amdgpu_sched_in in; > >>>>>>> }; > >>>>>>> > >>>>>>> +#define AMDGPU_SETPARAM_NO_IMPLICIT_SYNC 1 > >>>>>>> + > >>>>>>> +struct drm_amdgpu_setparam { > >>>>>>> + /* AMDGPU_SETPARAM_* */ > >>>>>>> + __u32 param; > >>>>>>> + __u32 value; > >>>>>>> +}; > >>>>>>> + > >>>>>>> /* > >>>>>>> * This is not a reliable API and you should expect it to fai= l for any > >>>>>>> * number of reasons and have fallback path that do not use u= serptr to > >>>>>>> -- > >>>>>>> 2.32.0.rc2 > >>>>>>> > > > --=20 Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD2F3C4743C for ; Wed, 23 Jun 2021 14:51:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9DAFD60041 for ; Wed, 23 Jun 2021 14:51:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9DAFD60041 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D9EB6E920; Wed, 23 Jun 2021 14:50:59 +0000 (UTC) Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38BF56E920 for ; Wed, 23 Jun 2021 14:50:58 +0000 (UTC) Received: by mail-ot1-x32e.google.com with SMTP id 6-20020a9d07860000b02903e83bf8f8fcso2147798oto.12 for ; Wed, 23 Jun 2021 07:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=mLK+t9vbBMf5eQK1453iefhEKkMWDs/+WdTBxGANbmU=; b=DQ4I6rKH4Sb7nUJ1kDBPVglIYR9klQ6uzr24M5E+IML8qk1fk8PczQU/yk60BWD4RD jc/ugGtks5sVbhFzbK+qS+3RFnPO+w5zOQ0HqMgapPsSnjPHZv+4IpMlxSiVoNpjwvNN oyaZwWHNS1/Zm2hgSLeoY8eYCuHwjqPJO0y3Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=mLK+t9vbBMf5eQK1453iefhEKkMWDs/+WdTBxGANbmU=; b=QkiFrO1BHj62XEQbbs8reFLvCGUsihF6ZGxUzNGbXeD7WTM9YzIk51fQK0qMIhcPf6 kPqsBuKQnc8uQxHsvH7LGkUdUgicT0CGy741hBXgpNoseSincLT+ypwZiHsFfSNyHkfE bW1A+ce9wlfmniQibWM01ppV80dpoXrrSwmhnpZgMsroF+u663Qkxa66BWoJgVZAHYdN vJSHbQkxVL0QltfyvSNUH/yQBQTieThGQVFrEyYAoOwD4ZXajuF2+RInZ6m9HxuUcDsk D8Xf0TMz1Uch7PKJ7GElPJyII4CpQFbVI6GUuYSVpdOJopX8cgB2fQDZK6/HcvOl7rWT wXbA== X-Gm-Message-State: AOAM532ilYwGaqBZSuQTv+a8/j8u4tLo3iJDz21qGUpMwm1laG+02cKI YJvSWIZp61cZ9T/PYT4ess55fHa7GkvAKCmCUDDEsNSGDTk= X-Google-Smtp-Source: ABdhPJwepdGBrzdDtB8NbnIjNfZukLgkURi/E6/D407xWoqeY1N/4o1WVrchBWB0lb87samOU9kH5E7Xa/sycejkvVU= X-Received: by 2002:a05:6830:2370:: with SMTP id r16mr261588oth.188.1624459857447; Wed, 23 Jun 2021 07:50:57 -0700 (PDT) MIME-Version: 1.0 References: <20210622165511.3169559-1-daniel.vetter@ffwll.ch> <20210622165511.3169559-16-daniel.vetter@ffwll.ch> <3bf45006-4256-763d-601b-3a25a7057820@amd.com> <421cb10d-92a7-0780-3d38-d4cabd008c0c@amd.com> <682d2f3b-8ba3-cccb-1385-1f74f0b06ada@amd.com> In-Reply-To: <682d2f3b-8ba3-cccb-1385-1f74f0b06ada@amd.com> From: Daniel Vetter Date: Wed, 23 Jun 2021 16:50:46 +0200 Message-ID: To: =?UTF-8?Q?Christian_K=C3=B6nig?= Subject: Re: [Intel-gfx] [PATCH 15/15] RFC: drm/amdgpu: Implement a proper implicit fencing uapi X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Daniel Stone , Daniel Vetter , Intel Graphics Development , Kevin Wang , DRI Development , Sumit Semwal , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Luben Tuikov , "Kristian H . Kristensen" , Chen Li , Bas Nieuwenhuizen , Alex Deucher , mesa-dev , Dave Airlie , =?UTF-8?Q?Michel_D=C3=A4nzer?= , Dennis Li , Deepak R Varma Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" T24gV2VkLCBKdW4gMjMsIDIwMjEgYXQgNDowMiBQTSBDaHJpc3RpYW4gS8O2bmlnCjxjaHJpc3Rp YW4ua29lbmlnQGFtZC5jb20+IHdyb3RlOgo+Cj4gQW0gMjMuMDYuMjEgdW0gMTU6NDkgc2Nocmll YiBEYW5pZWwgVmV0dGVyOgo+ID4gT24gV2VkLCBKdW4gMjMsIDIwMjEgYXQgMzo0NCBQTSBDaHJp c3RpYW4gS8O2bmlnCj4gPiA8Y2hyaXN0aWFuLmtvZW5pZ0BhbWQuY29tPiB3cm90ZToKPiA+PiBB bSAyMy4wNi4yMSB1bSAxNTozOCBzY2hyaWViIEJhcyBOaWV1d2VuaHVpemVuOgo+ID4+PiBPbiBX ZWQsIEp1biAyMywgMjAyMSBhdCAyOjU5IFBNIENocmlzdGlhbiBLw7ZuaWcKPiA+Pj4gPGNocmlz dGlhbi5rb2VuaWdAYW1kLmNvbT4gd3JvdGU6Cj4gPj4+PiBBbSAyMy4wNi4yMSB1bSAxNDoxOCBz Y2hyaWViIERhbmllbCBWZXR0ZXI6Cj4gPj4+Pj4gT24gV2VkLCBKdW4gMjMsIDIwMjEgYXQgMTE6 NDUgQU0gQmFzIE5pZXV3ZW5odWl6ZW4KPiA+Pj4+PiA8YmFzQGJhc25pZXV3ZW5odWl6ZW4ubmw+ IHdyb3RlOgo+ID4+Pj4+PiBPbiBUdWUsIEp1biAyMiwgMjAyMSBhdCA2OjU1IFBNIERhbmllbCBW ZXR0ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+IHdyb3RlOgo+ID4+Pj4+Pj4gV0FSTklORzog QWJzb2x1dGVseSB1bnRlc3RlZCBiZXlvbmQgImdjYyBpc24ndCBkeWluZyBpbiBhZ29ueSIuCj4g Pj4+Pj4+Pgo+ID4+Pj4+Pj4gSW1wbGljaXQgZmVuY2luZyBkb25lIHByb3Blcmx5IG5lZWRzIHRv IHRyZWF0IHRoZSBpbXBsaWNpdCBmZW5jaW5nCj4gPj4+Pj4+PiBzbG90cyBsaWtlIGEgZnVubnkg a2luZCBvZiBJUEMgbWFpbGJveC4gSW4gb3RoZXIgd29yZHMgaXQgbmVlZHMgdG8gYmUKPiA+Pj4+ Pj4+IGV4cGxpY2l0bHkuIFRoaXMgaXMgdGhlIG9ubHkgd2F5IGl0IHdpbGwgbWVzaCB3ZWxsIHdp dGggZXhwbGljaXQKPiA+Pj4+Pj4+IGZlbmNpbmcgdXNlcnNwYWNlIGxpa2UgdmssIGFuZCBpdCdz IGFsc28gdGhlIGJhcmUgbWluaW11bSByZXF1aXJlZCB0bwo+ID4+Pj4+Pj4gYmUgYWJsZSB0byBt YW5hZ2UgYW55dGhpbmcgZWxzZSB0aGF0IHdhbnRzIHRvIHVzZSB0aGUgc2FtZSBidWZmZXIgb24K PiA+Pj4+Pj4+IG11bHRpcGxlIGVuZ2luZXMgaW4gcGFyYWxsZWwsIGFuZCBzdGlsbCBiZSBhYmxl IHRvIHNoYXJlIGl0IHRocm91Z2gKPiA+Pj4+Pj4+IGltcGxpY2l0IHN5bmMuCj4gPj4+Pj4+Pgo+ ID4+Pj4+Pj4gYW1kZ3B1IGNvbXBsZXRlbHkgbGFja3Mgc3VjaCBhbiB1YXBpLiBGaXggdGhpcy4K PiA+Pj4+Pj4+Cj4gPj4+Pj4+PiBMdWNraWx5IHRoZSBjb25jZXB0IG9mIGlnbm9yaW5nIGltcGxp Y2l0IGZlbmNlcyBleGlzdHMgYWxyZWFkeSwgYW5kCj4gPj4+Pj4+PiB0YWtlcyBjYXJlIG9mIGFs bCB0aGUgY29tcGxleGl0aWVzIG9mIG1ha2luZyBzdXJlIHRoYXQgbm9uLW9wdGlvbmFsCj4gPj4+ Pj4+PiBmZW5jZXMgKGxpa2UgYm8gbW92ZXMpIGFyZSBub3QgaWdub3JlZC4gVGhpcyBzdXBwb3J0 IHdhcyBhZGRlZCBpbgo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+IGNvbW1pdCAxNzdhZTA5YjVkNjk5YTVl YmQxY2FmY2VlNzg4ODlkYjk2OGFiZjU0Cj4gPj4+Pj4+PiBBdXRob3I6IEFuZHJlcyBSb2RyaWd1 ZXogPGFuZHJlc3g3QGdtYWlsLmNvbT4KPiA+Pj4+Pj4+IERhdGU6ICAgRnJpIFNlcCAxNSAyMDo0 NDowNiAyMDE3IC0wNDAwCj4gPj4+Pj4+Pgo+ID4+Pj4+Pj4gICAgICAgIGRybS9hbWRncHU6IGlu dHJvZHVjZSBBTURHUFVfR0VNX0NSRUFURV9FWFBMSUNJVF9TWU5DIHYyCj4gPj4+Pj4+Pgo+ID4+ Pj4+Pj4gVW5mb3J0dWFudGVseSBpdCdzIHRoZSB3cm9uZyBzZW1hbnRpY3MsIGJlY2F1c2UgaXQn cyBhIGJvIGZsYWcgYW5kCj4gPj4+Pj4+PiBkaXNhYmxlcyBpbXBsaWNpdCBzeW5jIG9uIGFuIGFs bG9jYXRlZCBidWZmZXIgY29tcGxldGVseS4KPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiBXZSBfZG9fIHdh bnQgaW1wbGljaXQgc3luYywgYnV0IGNvbnRyb2wgaXQgZXhwbGljaXRseS4gRm9yIHRoaXMgd2UK PiA+Pj4+Pj4+IG5lZWQgYSBmbGFnIG9uIHRoZSBkcm1fZmlsZSwgc28gdGhhdCBhIGdpdmVuIHVz ZXJzcGFjZSAobGlrZSB2dWxrYW4pCj4gPj4+Pj4+PiBjYW4gbWFuYWdlIHRoZSBpbXBsaWNpdCBz eW5jIHNsb3RzIGV4cGxpY2l0bHkuIFRoZSBvdGhlciBzaWRlIG9mIHRoZQo+ID4+Pj4+Pj4gcGlw ZWxpbmUgKGNvbXBvc2l0b3IsIG90aGVyIHByb2Nlc3Mgb3IganVzdCBkaWZmZXJlbnQgc3RhZ2Ug aW4gYSBtZWRpYQo+ID4+Pj4+Pj4gcGlwZWxpbmUgaW4gdGhlIHNhbWUgcHJvY2VzcykgY2FuIHRo ZW4gZWl0aGVyIGRvIHRoZSBzYW1lLCBvciBmdWxseQo+ID4+Pj4+Pj4gcGFydGljaXBhdGUgaW4g dGhlIGltcGxpY2l0IHN5bmMgYXMgaW1wbGVtZW50ZWQgYnkgdGhlIGtlcm5lbCBieQo+ID4+Pj4+ Pj4gZGVmYXVsdC4KPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiBCeSBidWlsZGluZyBvbiB0aGUgZXhpc3Rp bmcgZmxhZyBmb3IgYnVmZmVycyB3ZSBhdm9pZCBhbnkgaXNzdWVzIHdpdGgKPiA+Pj4+Pj4+IG9w ZW5pbmcgdXAgYWRkaXRpb25hbCBzZWN1cml0eSBjb25jZXJucyAtIGFueXRoaW5nIHRoaXMgbmV3 IGZsYWcgaGVyZQo+ID4+Pj4+Pj4gYWxsb3dzIGlzIGFscmVhZHkuCj4gPj4+Pj4+Pgo+ID4+Pj4+ Pj4gQWxsIGRyaXZlcnMgd2hpY2ggc3VwcG9ydHMgdGhpcyBjb25jZXB0IG9mIGEgdXNlcnNwYWNl LXNwZWNpZmljCj4gPj4+Pj4+PiBvcHQtb3V0IG9mIGltcGxpY2l0IHN5bmMgaGF2ZSBhIGZsYWcg aW4gdGhlaXIgQ1MgaW9jdGwsIGJ1dCBpbiByZWFsaXR5Cj4gPj4+Pj4+PiB0aGF0IHR1cm5lZCBv dXQgdG8gYmUgYSBiaXQgdG9vIGluZmxleGlibGUuIFNlZSB0aGUgZGlzY3Vzc2lvbiBiZWxvdywK PiA+Pj4+Pj4+IGxldCdzIHRyeSB0byBkbyBhIGJpdCBiZXR0ZXIgZm9yIGFtZGdwdS4KPiA+Pj4+ Pj4+Cj4gPj4+Pj4+PiBUaGlzIGFsb25lIG9ubHkgYWxsb3dzIHVzIHRvIGNvbXBsZXRlbHkgYXZv aWQgYW55IHN0YWxscyBkdWUgdG8KPiA+Pj4+Pj4+IGltcGxpY2l0IHN5bmMsIGl0IGRvZXMgbm90 IHlldCBhbGxvdyB1cyB0byB1c2UgaW1wbGljaXQgc3luYyBhcyBhCj4gPj4+Pj4+PiBzdHJhbmdl IGZvcm0gb2YgSVBDIGZvciBzeW5jX2ZpbGUuCj4gPj4+Pj4+Pgo+ID4+Pj4+Pj4gRm9yIHRoYXQg d2UgbmVlZCB0d28gbW9yZSBwaWVjZXM6Cj4gPj4+Pj4+Pgo+ID4+Pj4+Pj4gLSBhIHdheSB0byBn ZXQgdGhlIGN1cnJlbnQgaW1wbGljaXQgc3luYyBmZW5jZXMgb3V0IG9mIGEgYnVmZmVyLiBDb3Vs ZAo+ID4+Pj4+Pj4gICAgICBiZSBkb25lIGluIGEgZHJpdmVyIGlvY3RsLCBidXQgZXZlcnlvbmUg bmVlZHMgdGhpcywgYW5kIGdlbmVyYWxseSBhCj4gPj4+Pj4+PiAgICAgIGRtYS1idWYgaXMgaW52 b2x2ZWQgYW55d2F5IHRvIGVzdGFibGlzaCB0aGUgc2hhcmluZy4gU28gYW4gaW9jdGwgb24KPiA+ Pj4+Pj4+ICAgICAgdGhlIGRtYS1idWYgbWFrZXMgYSB0b24gbW9yZSBzZW5zZToKPiA+Pj4+Pj4+ Cj4gPj4+Pj4+PiAgICAgIGh0dHBzOi8vbmFtMTEuc2FmZWxpbmtzLnByb3RlY3Rpb24ub3V0bG9v ay5jb20vP3VybD1odHRwcyUzQSUyRiUyRmxvcmUua2VybmVsLm9yZyUyRmRyaS1kZXZlbCUyRjIw MjEwNTIwMTkwMDA3LjUzNDA0Ni00LWphc29uJTQwamxla3N0cmFuZC5uZXQlMkYmYW1wO2RhdGE9 MDQlN0MwMSU3Q2NocmlzdGlhbi5rb2VuaWclNDBhbWQuY29tJTdDODNkYmRkMGExZWI4NDQyY2Jm NzEwOGQ5MzY0ZGI1MWUlN0MzZGQ4OTYxZmU0ODg0ZTYwOGUxMWE4MmQ5OTRlMTgzZCU3QzAlN0Mw JTdDNjM3NjAwNTI5Njg0MDQwODAyJTdDVW5rbm93biU3Q1RXRnBiR1pzYjNkOGV5SldJam9pTUM0 d0xqQXdNREFpTENKUUlqb2lWMmx1TXpJaUxDSkJUaUk2SWsxaGFXd2lMQ0pYVkNJNk1uMCUzRCU3 QzEwMDAmYW1wO3NkYXRhPWZiZHd0dXRFajkzYW5acDZQc2hzMjc3UW9NVEhaeEl5MFlsNTRUOTVy Q3clM0QmYW1wO3Jlc2VydmVkPTAKPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiAgICAgIEN1cnJlbnQgZHJp dmVycyBpbiB1cHN0cmVhbSBzb2x2ZXMgdGhpcyBieSBoYXZpbmcgdGhlIG9wdC1vdXQgZmxhZwo+ ID4+Pj4+Pj4gICAgICBvbiB0aGVpciBDUyBpb2N0bC4gVGhpcyBoYXMgdGhlIGRvd25zaWRlIHRo YXQgdmVyeSBvZnRlbiB0aGUgQ1MKPiA+Pj4+Pj4+ICAgICAgd2hpY2ggbXVzdCBhY3R1YWxseSBz dGFsbCBmb3IgdGhlIGltcGxpY2l0IGZlbmNlIGlzIHJ1biBhIHdoaWxlCj4gPj4+Pj4+PiAgICAg IGFmdGVyIHRoZSBpbXBsaWNpdCBmZW5jZSBwb2ludCB3YXMgbG9naWNhbGx5IHNhbXBsZWQgcGVy IHRoZSBhcGkKPiA+Pj4+Pj4+ICAgICAgc3BlYyAodmsgcGFzc2VzIGFuIGV4cGxpY2l0IHN5bmNv YmogYXJvdW5kIGZvciB0aGF0IGFmYWl1aSksIGFuZCBzbwo+ID4+Pj4+Pj4gICAgICByZXN1bHRz IGluIG92ZXJzeW5jLiBDb252ZXJ0aW5nIHRoZSBpbXBsaWNpdCBzeW5jIGZlbmNlcyBpbnRvIGEK PiA+Pj4+Pj4+ICAgICAgc25hcC1zaG90IHN5bmNfZmlsZSBpcyBhY3R1YWxseSBhY2N1cmF0ZS4K PiA+Pj4+Pj4+Cj4gPj4+Pj4+PiAtIFNpbWlsbGFyIHdlIG5lZWQgdG8gYmUgYWJsZSB0byBzZXQg dGhlIGV4Y2x1c2l2ZSBpbXBsaWNpdCBmZW5jZS4KPiA+Pj4+Pj4+ICAgICAgQ3VycmVudCBkcml2 ZXJzIGFnYWluIGRvIHRoaXMgd2l0aCBhIENTIGlvY3RsIGZsYWcsIHdpdGggYWdhaW4gdGhlCj4g Pj4+Pj4+PiAgICAgIHNhbWUgcHJvYmxlbXMgdGhhdCB0aGUgdGltZSB0aGUgQ1MgaGFwcGVucyBh ZGRpdGlvbmFsIGRlcGVuZGVuY2llcwo+ID4+Pj4+Pj4gICAgICBoYXZlIGJlZW4gYWRkZWQuIEFu IGV4cGxpY2l0IGlvY3RsIHRvIG9ubHkgaW5zZXJ0IGEgc3luY19maWxlICh3aGlsZQo+ID4+Pj4+ Pj4gICAgICByZXNwZWN0aW5nIHRoZSBydWxlcyBmb3IgaG93IGV4Y2x1c2l2ZSBhbmQgc2hhcmVk IGZlbmNlIHNsb3RzIG11c3QKPiA+Pj4+Pj4+ICAgICAgYmUgdXBkYXRlIGluIHN0cnVjdCBkbWFf cmVzdikgaXMgbXVjaCBiZXR0ZXIuIFRoaXMgaXMgcHJvcG9zZWQgaGVyZToKPiA+Pj4+Pj4+Cj4g Pj4+Pj4+PiAgICAgIGh0dHBzOi8vbmFtMTEuc2FmZWxpbmtzLnByb3RlY3Rpb24ub3V0bG9vay5j b20vP3VybD1odHRwcyUzQSUyRiUyRmxvcmUua2VybmVsLm9yZyUyRmRyaS1kZXZlbCUyRjIwMjEw NTIwMTkwMDA3LjUzNDA0Ni01LWphc29uJTQwamxla3N0cmFuZC5uZXQlMkYmYW1wO2RhdGE9MDQl N0MwMSU3Q2NocmlzdGlhbi5rb2VuaWclNDBhbWQuY29tJTdDODNkYmRkMGExZWI4NDQyY2JmNzEw OGQ5MzY0ZGI1MWUlN0MzZGQ4OTYxZmU0ODg0ZTYwOGUxMWE4MmQ5OTRlMTgzZCU3QzAlN0MwJTdD NjM3NjAwNTI5Njg0MDQwODAyJTdDVW5rbm93biU3Q1RXRnBiR1pzYjNkOGV5SldJam9pTUM0d0xq QXdNREFpTENKUUlqb2lWMmx1TXpJaUxDSkJUaUk2SWsxaGFXd2lMQ0pYVkNJNk1uMCUzRCU3QzEw MDAmYW1wO3NkYXRhPXZ2JTJCUkVuV29yam9UT3dyRDFqSDFHSFZRY2pQeTFvZXNhb3Boc3owNTZh SSUzRCZhbXA7cmVzZXJ2ZWQ9MAo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+IFRoZXNlIHRocmVlIHBpZWNl cyB0b2dldGhlciBhbGxvdyB1c2Vyc3BhY2UgdG8gZnVsbHkgY29udHJvbCBpbXBsaWNpdAo+ID4+ Pj4+Pj4gZmVuY2luZyBhbmQgcmVtb3ZlIGFsbCB1bmVjZXNzYXJ5IHN0YWxsIHBvaW50cyBkdWUg dG8gdGhlbS4KPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiBXZWxsLCBhcyBtdWNoIGFzIHRoZSBpbXBsaWNp dCBmZW5jaW5nIG1vZGVsIGZ1bmRhbWVudGFsbHkgYWxsb3dzOgo+ID4+Pj4+Pj4gVGhlcmUgaXMg b25seSBvbmUgc2V0IG9mIGZlbmNlcywgeW91IGNhbiBvbmx5IGNob29zZSB0byBzeW5jIGFnYWlu c3QKPiA+Pj4+Pj4+IG9ubHkgd3JpdGVycyAoZXhjbHVzaXZlIHNsb3QpLCBvciBldmVyeW9uZS4g SGVuY2Ugc3ViYWxsb2NhdGluZwo+ID4+Pj4+Pj4gbXVsdGlwbGUgYnVmZmVycyBvciBhbnl0aGlu ZyBlbHNlIGxpa2UgdGhpcyBpcyBmdW5kYW1lbnRhbGx5IG5vdAo+ID4+Pj4+Pj4gcG9zc2libGUs IGFuZCBjYW4gb25seSBiZSBmaXhlZCBieSBhIHByb3BlciBleHBsaWNpdCBmZW5jaW5nIG1vZGVs Lgo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+IEFzaWRlIGZyb20gdGhhdCBjYXZlYXQgdGhpcyBtb2RlbCBn ZXRzIGltcGxpY2l0IGZlbmNpbmcgYXMgY2xvc2VseSB0bwo+ID4+Pj4+Pj4gZXhwbGljaXQgZmVu Y2luZyBzZW1hbnRpY3MgYXMgcG9zc2libGU6Cj4gPj4+Pj4+Pgo+ID4+Pj4+Pj4gT24gdGhlIGFj dHVhbCBpbXBsZW1lbnRhdGlvbiBJIG9wdGVkIGZvciBhIHNpbXBsZSBzZXRwYXJhbSBpb2N0bCwg bm8KPiA+Pj4+Pj4+IGxvY2tpbmcgKGp1c3QgYXRvbWljIHJlYWRzL3dyaXRlcykgZm9yIHNpbXBs aWNpdHkuIFRoZXJlIGlzIGEgbmljZQo+ID4+Pj4+Pj4gZmxhZyBwYXJhbWV0ZXIgaW4gdGhlIFZN IGlvY3RsIHdoaWNoIHdlIGNvdWxkIHVzZSwgZXhjZXB0Ogo+ID4+Pj4+Pj4gLSBpdCdzIG5vdCBj aGVja2VkLCBzbyB1c2Vyc3BhY2UgbGlrZWx5IHBhc3NlcyBnYXJiYWdlCj4gPj4+Pj4+PiAtIHRo ZXJlJ3MgYWxyZWFkeSBhIGNvbW1lbnQgdGhhdCB1c2Vyc3BhY2UgX2RvZXNfIHBhc3MgZ2FyYmFn ZSBpbiB0aGUKPiA+Pj4+Pj4+ICAgICAgcHJpb3JpdHkgZmllbGQKPiA+Pj4+Pj4+IFNvIHllYWgg dW5mb3J0dW5hdGVseSB0aGlzIGZsYWcgcGFyYW1ldGVyIGZvciBzZXR0aW5nIHZtIGZsYWdzIGlz Cj4gPj4+Pj4+PiB1c2VsZXNzLCBhbmQgd2UgbmVlZCB0byBoYWNrIHVwIGEgbmV3IG9uZS4KPiA+ Pj4+Pj4+Cj4gPj4+Pj4+PiB2MjogRXhwbGFpbiB3aHkgYSBuZXcgU0VUUEFSQU0gKEphc29uKQo+ ID4+Pj4+Pj4KPiA+Pj4+Pj4+IHYzOiBCYXMgbm90aWNlZCBJIGZvcmdvdCB0byBob29rIHVwIHRo ZSBkZXBlbmRlbmN5LXNpZGUgc2hvcnRjdXQuIFdlCj4gPj4+Pj4+PiBuZWVkIGJvdGgsIG9yIHRo aXMgZG9lc24ndCBkbyBtdWNoLgo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+IHY0OiBSZWJhc2Ugb3ZlciB0 aGUgYW1kZ3B1IHBhdGNoIHRvIGFsd2F5cyBzZXQgdGhlIGltcGxpY2l0IHN5bmMKPiA+Pj4+Pj4+ IGZlbmNlcy4KPiA+Pj4+Pj4gU28gSSB0aGluayB0aGVyZSBpcyBzdGlsbCBhIGNhc2UgbWlzc2lu ZyBpbiB0aGlzIGltcGxlbWVudGF0aW9uLgo+ID4+Pj4+PiBDb25zaWRlciB0aGVzZSAzIGNhc2Vz Cj4gPj4+Pj4+Cj4gPj4+Pj4+IChmb3JtYXQ6IGEtPmI6IGIgd2FpdHMgb24gYS4gWWVzLCBJIGtu b3cgYXJyb3dzIGFyZSBoYXJkKQo+ID4+Pj4+Pgo+ID4+Pj4+PiBleHBsaWNpdC0+ZXhwbGljaXQ6 IFRoaXMgZG9lc24ndCB3YWl0IG5vdywgd2hpY2ggaXMgZ29vZAo+ID4+Pj4+PiBJbXBsaWNpdC0+ ZXhwbGljaXQ6IFRoaXMgZG9lc24ndCB3YWl0IG5vdywgd2hpY2ggaXMgZ29vZAo+ID4+Pj4+PiBl eHBsaWNpdC0+aW1wbGljaXQgOiBUaGlzIHN0aWxsIHdhaXRzIGFzIHRoZSBleHBsaWNpdCBzdWJt aXNzaW9uIHN0aWxsCj4gPj4+Pj4+IGFkZHMgc2hhcmVkIGZlbmNlcyBhbmQgbW9zdCB0aGluZ3Mg dGhhdCBzZXQgYW4gZXhjbHVzaXZlIGZlbmNlIGZvcgo+ID4+Pj4+PiBpbXBsaWNpdCBzeW5jIHdp bGwgaGVuY2Ugd2FpdCBvbiBpdC4KPiA+Pj4+Pj4KPiA+Pj4+Pj4gVGhpcyBpcyBwcm9iYWJseSBn b29kIGVub3VnaCBmb3Igd2hhdCByYWR2IG5lZWRzIG5vdyBidXQgYWxzbyBzb3VuZHMKPiA+Pj4+ Pj4gbGlrZSBhIHJpc2sgd3J0IGJha2luZyBpbiBuZXcgdWFwaSBiZWhhdmlvciB0aGF0IHdlIGRv bid0IHdhbnQgdG8gYmUKPiA+Pj4+Pj4gdGhlIGVuZCByZXN1bHQuCj4gPj4+Pj4+Cj4gPj4+Pj4+ IFdpdGhpbiBBTURHUFUgdGhpcyBpcyBwcm9iYWJseSBzb2x2YWJsZSBpbiB0d28gd2F5czoKPiA+ Pj4+Pj4KPiA+Pj4+Pj4gMSkgRG93bmdyYWRlIEFNREdQVV9TWU5DX05FX09XTkVSIHRvIEFNREdQ VV9TWU5DX0VYUExJQ0lUIGZvciBzaGFyZWQgZmVuY2VzLgo+ID4+Pj4+IEknbSBub3Qgc3VyZSB0 aGF0IHdvcmtzLiBJIHRoaW5rIHRoZSByaWdodCBmaXggaXMgdGhhdCByYWRlb25zaSBhbHNvCj4g Pj4+Pj4gc3dpdGNoZXMgdG8gdGhpcyBtb2RlbCwgd2l0aCBtYXliZSBhIHBlci1ibyBDUyBmbGFn IHRvIHNldCBpbmRpY2F0ZQo+ID4+Pj4+IHdyaXRlIGFjY2VzcywgdG8gY3V0IGRvd24gb24gdGhl IG51bWJlciBvZiBpb2N0bHMgdGhhdCBhcmUgbmVlZGVkCj4gPj4+Pj4gb3RoZXJ3aXNlIG9uIHNo YXJlZCBidWZmZXJzLiBUaGlzIHBlci1ibyBmbGFnIHdvdWxkIGVzc2VudGlhbGx5IHNlbGVjdAo+ ID4+Pj4+IGJldHdlZW4gU1lOQ19ORV9PV05FUiBhbmQgU1lOQ19FWFBMSUNJVCBvbiBhIHBlci1i dWZmZXIgYmFzaXMuCj4gPj4+PiBZZWFoLCBidXQgSSdtIHN0aWxsIG5vdCBlbnRpcmVseSBzdXJl IHdoeSB0aGF0IGFwcHJvYWNoIGlzbid0IHN1ZmZpY2llbnQ/Cj4gPj4+Pgo+ID4+Pj4gUHJvYmxl bSB3aXRoIHRoZSBwZXIgY29udGV4dCBvciBwZXIgdm0gZmxhZyBpcyB0aGF0IHlvdSB0aGVuIGRv bid0IGdldAo+ID4+Pj4gYW55IGltcGxpY2l0IHN5bmNocm9uaXphdGlvbiBhbnkgbW9yZSB3aGVu IGFub3RoZXIgcHJvY2VzcyBzdGFydHMgdXNpbmcKPiA+Pj4+IHRoZSBidWZmZXIuCj4gPj4+IFRo YXQgaXMgZXhhY3RseSB3aGF0IEkgd2FudCBmb3IgVnVsa2FuIDopCj4gPj4gWWVhaCwgYnV0IGFz IGZhciBhcyBJIGtub3cgdGhpcyBpcyBub3Qgc29tZXRoaW5nIHdlIGNhbiBkby4KPiA+Pgo+ID4+ IFNlZSB3ZSBoYXZlIHVzZSBjYXNlcyBsaWtlIHNjcmVlbiBjYXB0dXJlIGFuZCBkZWJ1ZyB3aGlj aCByZWx5IG9uIHRoYXQKPiA+PiBiZWhhdmlvci4KPiA+IFRoZXkgd2lsbCBrZWVwIHdvcmtpbmcs IGlmIChhbmQgb25seSBpZikgdGhlIHZ1bGthbiBzaWRlIHNldHMgdGhlCj4gPiB3aW5zeXMgZmVu Y2VzIGNvcnJlY3RseS4gQWxzbywgZXZlcnl0aGluZyBlbHNlIGluIHZ1bGthbiBhc2lkZSBmcm9t Cj4gPiB3aW5zeXMgaXMgZXhwbGljaXRseSBub3Qgc3luY2VkIGF0IGFsbCwgeW91IGhhdmUgdG8g aW1wb3J0IGRybSBzeW5jb2JqCj4gPiB0aW1lbGluZSBvbiB0aGUgZ2wgc2lkZS4KPiA+Cj4gPj4g VGhlIG9ubHkgdGhpbmcgd2UgY2FuIGRvIGlzIHRvIHNheSBvbiBhIHBlciBidWZmZXIgZmxhZyB0 aGF0IGEgYnVmZmVyCj4gPj4gc2hvdWxkIG5vdCBwYXJ0aWNpcGF0ZSBpbiBpbXBsaWNpdCBzeW5j IGF0IGFsbC4KPiA+IE5haCwgdGhpcyBkb2Vzbid0IHdvcmsuIEJlY2F1c2UgaXQncyBub3QgYSBn bG9iYWwgZGVjaXNpb24sIGlzIGEgbG9jYWwKPiA+IGRlY2lzaW9uIGZvciB0aGUgcmVuZGVyZWQu IFZ1bGthbiB3YW50cyB0byBjb250cm9sIGltcGxpY2l0IHN5bmMKPiA+IGV4cGxpY2l0bHksIGFu ZCB0aGUga2VybmVsIGNhbid0IGZvcmNlIG1vcmUgc3luY2hyb25pemF0aW9uLiBJZiBhCj4gPiBi dWZmZXIgaXMgc2hhcmVkIGFzIGEgd2luc3lzIGJ1ZmZlciBiZXR3ZWVuIHZ1bGthbiBjbGllbnQg YW5kIGdsIHVzaW5nCj4gPiBjb21wb3NpdG9yLCB0aGVuIHlvdSBfaGF2ZV8gdG8gdXNlIGltcGxp Y2l0IHN5bmMgb24gaXQuIEJ1dCB2ayBuZWVkcwo+ID4gdG8gc2V0IHRoZSBmZW5jZXMgZGlyZWN0 bHkgKGFuZCBpZiB0aGUgYXBwIGdldHMgaXQgd3JvbmcsIHlvdSBnZXQKPiA+IG1pc3JlbmRlcmlu ZywgYnV0IHRoYXQgaXMgdGhlIHNwZWNpZmllZCBiZWhhdm91ciBvZiB2dWxrYW4pLgo+Cj4gWWVh aCwgYnV0IHRoYXQncyBleGFjdGx5IHdoYXQgd2UgdHJpZWQgdG8gYXZvaWQuCj4KPiBNaG0sIHdo ZW4gd2UgYXR0YWNoIHRoZSBmbGFnIHRvIHRoZSBwcm9jZXNzL1ZNIHRoZW4gdGhpcyB3b3VsZCBi cmVhayB0aGUKPiB1c2UgY2FzZSBvZiBWQS1BUEkgYW5kIFZ1bGthbiBpbiB0aGUgc2FtZSBwcm9j ZXNzLgo+Cj4gQnV0IEkgdGhpbmsgaWYgeW91IGF0dGFjaCB0aGUgZmxhZyB0byB0aGUgY29udGV4 dCB0aGF0IHNob3VsZCBpbmRlZWQKPiB3b3JrIGZpbmUuCgpZZWFoIHRoYXQncyBhIHF1ZXN0aW9u IEkgaGF2ZSwgd2hldGhlciB0aGUgZHJtX2ZpbGUgaXMgc2hhcmVkIHdpdGhpbgpvbmUgcHJvY2Vz cyBhbW9uZyBldmVyeXRoaW5nLCBvciB3aGV0aGVyIHJhZGVvbnNpL2xpYnZhL3ZrIGVhY2ggaGF2 ZQp0aGVpciBvd24uIElmIGVhY2ggaGF2ZSB0aGVpciBvd24gZHJtX2ZpbGUsIHRoZW4gd2Ugc2hv dWxkIGJlIGZpbmUsCm90aGVyd2lzZSB3ZSBuZWVkIHRvIGZpZ3VyZSBvdXQgYW5vdGhlciBwbGFj ZSB0byBwdXQgdGhpcyAod29yc3QgY2FzZQphcyBhIENTIGV4dGVuc2lvbiB0aGF0IHZrIGp1c3Qg c2V0cyBvbiBldmVyeSBzdWJtaXQpLgoKQWxzbyB5ZXMgdGhpcyByaXNrcyB0aGF0IGEgdmsgYXBw IHdoaWNoIHdhcyB2aW9sYXRpb25pbmcgdGhlIHdpbnN5cwpzcGVjIHdpbGwgbm93IGJyZWFrLCB3 aGljaCBpcyB3aHkgSSB0aGluayB3ZSBzaG91bGQgZG8gdGhpcyBzb29uZXIKdGhhbiBsYXRlci4g T3RoZXJ3aXNlIHRoZSBsaXN0IG9mIHcvYSB3ZSBtaWdodCBuZWVkIHRvIGFwcGx5IGluIHZrCnVz ZXJzcGFjZSB3aWxsIGJlY29tZSB2ZXJ5IGxvbmcgOi0oIEF0IGxlYXN0IHNpbmNlIHRoaXMgaXMg cHVyZWx5Cm9wdC1pbiBmcm9tIHVzZXJzcGFjZSwgd2Ugb25seSBuZWVkIHRvIGhhdmUgdGhlIHcv YSBsaXN0IGluIHVzZXJzcGFjZSwKd2hlcmUgbWVzYSBoYXMgdGhlIGluZnJhc3RydWN0dXJlIGZv ciB0aGF0IGFscmVhZHkuCi1EYW5pZWwKCj4KPiBDaHJpc3RpYW4uCj4KPiA+IC1EYW5pZWwKPiA+ Cj4gPj4gUmVnYXJkcywKPiA+PiBDaHJpc3RpYW4uCj4gPj4KPiA+Pj4+PiBUaGUgY3VycmVudCBh bWRncHUgdWFwaSBqdXN0IGRvZXNuJ3QgYWxsb3cgYW55IG90aGVyIG1vZGVsIHdpdGhvdXQgYW4K PiA+Pj4+PiBleHBsaWNpdCBvcHQtaW4uIFNvIGN1cnJlbnQgaW1wbGljaXQgc3luYyB1c2Vyc3Bh Y2UganVzdCBoYXMgdG8KPiA+Pj4+PiBvdmVyc3luYywgdGhlcmUncyBub3QgbXVjaCBjaG9pY2Uu Cj4gPj4+Pj4KPiA+Pj4+Pj4gMikgSGF2ZSBhbiBFWFBMSUNJVCBmZW5jZSBvd25lciB0aGF0IGlz IHVzZWQgZm9yIGV4cGxpY2l0IHN1Ym1pc3Npb25zCj4gPj4+Pj4+IHRoYXQgaXMgaWdub3JlZCBi eSBBTURHUFVfU1lOQ19ORV9PV05FUi4KPiA+Pj4+Pj4KPiA+Pj4+Pj4gQnV0IHRoaXMgZG9lc24n dCBzb2x2ZSBjcm9zcy1kcml2ZXIgaW50ZXJhY3Rpb25zIGhlcmUuCj4gPj4+Pj4gWWVhaCBjcm9z cy1kcml2ZXIgaXMgc3RpbGwgZW50aXJlbHkgdW5zb2x2ZWQsIGJlY2F1c2UKPiA+Pj4+PiBhbWRn cHVfYm9fZXhwbGljaXRfc3luYygpIG9uIHRoZSBibyBkaWRuJ3Qgc29sdmUgdGhhdCBlaXRoZXIu Cj4gPj4+PiBIdWk/IFlvdSBoYXZlIGxvc3QgbWUuIFdoeSBpcyB0aGF0IHN0aWxsIHVuc29sdmVk Pwo+ID4+PiBUaGUgcGFydCB3ZSdyZSB0cnlpbmcgdG8gc29sdmUgd2l0aCB0aGlzIHBhdGNoIGlz IFZ1bGthbiBzaG91bGQgbm90Cj4gPj4+IHBhcnRpY2lwYXRlIGluIGFueSBpbXBsaWNpdCBzeW5j IGF0IGFsbCB3cnQgc3VibWlzc2lvbnMgKGFuZCB0aGVuCj4gPj4+IGhhbmRsZSB0aGUgaW1wbGlj aXQgc3luYyBmb3IgV1NJIGV4cGxpY2l0bHkgdXNpbmcgdGhlIGZlbmNlCj4gPj4+IGltcG9ydC9l eHBvcnQgc3R1ZmYgdGhhdCBKYXNvbiB3cm90ZSkuIEFzIGxvbmcgd2UgYWRkIHNoYXJlZCBmZW5j ZXMgdG8KPiA+Pj4gdGhlIGRtYV9yZXN2IHdlIHBhcnRpY2lwYXRlIGluIGltcGxpY2l0IHN5bmMg KGF0IHRoZSBsZXZlbCBvZiBhbgo+ID4+PiBpbXBsaWNpdCBzeW5jIHJlYWQpIHN0aWxsLCBhdCBs ZWFzdCBmcm9tIHRoZSBwZXJzcGVjdGl2ZSBvZiBsYXRlciBqb2JzCj4gPj4+IHdhaXRpbmcgb24g dGhlc2UgZmVuY2VzLgo+ID4+Pgo+ID4+Pj4gUmVnYXJkcywKPiA+Pj4+IENocmlzdGlhbi4KPiA+ Pj4+Cj4gPj4+Pj4gLURhbmllbAo+ID4+Pj4+Cj4gPj4+Pj4+PiBDYzogbWVzYS1kZXZAbGlzdHMu ZnJlZWRlc2t0b3Aub3JnCj4gPj4+Pj4+PiBDYzogQmFzIE5pZXV3ZW5odWl6ZW4gPGJhc0BiYXNu aWV1d2VuaHVpemVuLm5sPgo+ID4+Pj4+Pj4gQ2M6IERhdmUgQWlybGllIDxhaXJsaWVkQGdtYWls LmNvbT4KPiA+Pj4+Pj4+IENjOiBSb2IgQ2xhcmsgPHJvYmRjbGFya0BjaHJvbWl1bS5vcmc+Cj4g Pj4+Pj4+PiBDYzogS3Jpc3RpYW4gSC4gS3Jpc3RlbnNlbiA8aG9lZ3NiZXJnQGdvb2dsZS5jb20+ Cj4gPj4+Pj4+PiBDYzogTWljaGVsIETDpG56ZXIgPG1pY2hlbEBkYWVuemVyLm5ldD4KPiA+Pj4+ Pj4+IENjOiBEYW5pZWwgU3RvbmUgPGRhbmllbHNAY29sbGFib3JhLmNvbT4KPiA+Pj4+Pj4+IENj OiBTdW1pdCBTZW13YWwgPHN1bWl0LnNlbXdhbEBsaW5hcm8ub3JnPgo+ID4+Pj4+Pj4gQ2M6ICJD aHJpc3RpYW4gS8O2bmlnIiA8Y2hyaXN0aWFuLmtvZW5pZ0BhbWQuY29tPgo+ID4+Pj4+Pj4gQ2M6 IEFsZXggRGV1Y2hlciA8YWxleGFuZGVyLmRldWNoZXJAYW1kLmNvbT4KPiA+Pj4+Pj4+IENjOiBE YW5pZWwgVmV0dGVyIDxkYW5pZWwudmV0dGVyQGZmd2xsLmNoPgo+ID4+Pj4+Pj4gQ2M6IERlZXBh ayBSIFZhcm1hIDxtaDEyZ3gyODI1QGdtYWlsLmNvbT4KPiA+Pj4+Pj4+IENjOiBDaGVuIExpIDxj aGVubGlAdW5pb250ZWNoLmNvbT4KPiA+Pj4+Pj4+IENjOiBLZXZpbiBXYW5nIDxrZXZpbjEud2Fu Z0BhbWQuY29tPgo+ID4+Pj4+Pj4gQ2M6IERlbm5pcyBMaSA8RGVubmlzLkxpQGFtZC5jb20+Cj4g Pj4+Pj4+PiBDYzogTHViZW4gVHVpa292IDxsdWJlbi50dWlrb3ZAYW1kLmNvbT4KPiA+Pj4+Pj4+ IENjOiBsaW5hcm8tbW0tc2lnQGxpc3RzLmxpbmFyby5vcmcKPiA+Pj4+Pj4+IFNpZ25lZC1vZmYt Ynk6IERhbmllbCBWZXR0ZXIgPGRhbmllbC52ZXR0ZXJAaW50ZWwuY29tPgo+ID4+Pj4+Pj4gLS0t Cj4gPj4+Pj4+PiAgICAgZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvYW1kZ3B1X2NzLmMgIHwg IDcgKysrKystLQo+ID4+Pj4+Pj4gICAgIGRyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2FtZGdw dV9kcnYuYyB8IDIxICsrKysrKysrKysrKysrKysrKysrKwo+ID4+Pj4+Pj4gICAgIGRyaXZlcnMv Z3B1L2RybS9hbWQvYW1kZ3B1L2FtZGdwdV92bS5oICB8ICA2ICsrKysrKwo+ID4+Pj4+Pj4gICAg IGluY2x1ZGUvdWFwaS9kcm0vYW1kZ3B1X2RybS5oICAgICAgICAgICB8IDEwICsrKysrKysrKysK PiA+Pj4+Pj4+ICAgICA0IGZpbGVzIGNoYW5nZWQsIDQyIGluc2VydGlvbnMoKyksIDIgZGVsZXRp b25zKC0pCj4gPj4+Pj4+Pgo+ID4+Pj4+Pj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9h bWQvYW1kZ3B1L2FtZGdwdV9jcy5jIGIvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvYW1kZ3B1 X2NzLmMKPiA+Pj4+Pj4+IGluZGV4IDY1ZGYzNGMxNzI2NC4uYzUzODZkMTNlYjRhIDEwMDY0NAo+ ID4+Pj4+Pj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvYW1kZ3B1X2NzLmMKPiA+ Pj4+Pj4+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2FtZGdwdV9jcy5jCj4gPj4+ Pj4+PiBAQCAtNDk4LDYgKzQ5OCw3IEBAIHN0YXRpYyBpbnQgYW1kZ3B1X2NzX3BhcnNlcl9ib3Mo c3RydWN0IGFtZGdwdV9jc19wYXJzZXIgKnAsCj4gPj4+Pj4+PiAgICAgICAgICAgIHN0cnVjdCBh bWRncHVfYm8gKmdkczsKPiA+Pj4+Pj4+ICAgICAgICAgICAgc3RydWN0IGFtZGdwdV9ibyAqZ3dz Owo+ID4+Pj4+Pj4gICAgICAgICAgICBzdHJ1Y3QgYW1kZ3B1X2JvICpvYTsKPiA+Pj4+Pj4+ICsg ICAgICAgYm9vbCBub19pbXBsaWNpdF9zeW5jID0gUkVBRF9PTkNFKGZwcml2LT52bS5ub19pbXBs aWNpdF9zeW5jKTsKPiA+Pj4+Pj4+ICAgICAgICAgICAgaW50IHI7Cj4gPj4+Pj4+Pgo+ID4+Pj4+ Pj4gICAgICAgICAgICBJTklUX0xJU1RfSEVBRCgmcC0+dmFsaWRhdGVkKTsKPiA+Pj4+Pj4+IEBA IC01NzcsNyArNTc4LDggQEAgc3RhdGljIGludCBhbWRncHVfY3NfcGFyc2VyX2JvcyhzdHJ1Y3Qg YW1kZ3B1X2NzX3BhcnNlciAqcCwKPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiAgICAgICAgICAgICAgICAg ICAgZS0+Ym9fdmEgPSBhbWRncHVfdm1fYm9fZmluZCh2bSwgYm8pOwo+ID4+Pj4+Pj4KPiA+Pj4+ Pj4+IC0gICAgICAgICAgICAgICBpZiAoYm8tPnRiby5iYXNlLmRtYV9idWYgJiYgIWFtZGdwdV9i b19leHBsaWNpdF9zeW5jKGJvKSkgewo+ID4+Pj4+Pj4gKyAgICAgICAgICAgICAgIGlmIChiby0+ dGJvLmJhc2UuZG1hX2J1ZiAmJgo+ID4+Pj4+Pj4gKyAgICAgICAgICAgICAgICAgICAhKG5vX2lt cGxpY2l0X3N5bmMgfHwgYW1kZ3B1X2JvX2V4cGxpY2l0X3N5bmMoYm8pKSkgewo+ID4+Pj4+Pj4g ICAgICAgICAgICAgICAgICAgICAgICAgICAgZS0+Y2hhaW4gPSBkbWFfZmVuY2VfY2hhaW5fYWxs b2MoKTsKPiA+Pj4+Pj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgIGlmICghZS0+Y2hhaW4p IHsKPiA+Pj4+Pj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgciA9IC1FTk9N RU07Cj4gPj4+Pj4+PiBAQCAtNjQ5LDYgKzY1MSw3IEBAIHN0YXRpYyBpbnQgYW1kZ3B1X2NzX3N5 bmNfcmluZ3Moc3RydWN0IGFtZGdwdV9jc19wYXJzZXIgKnApCj4gPj4+Pj4+PiAgICAgewo+ID4+ Pj4+Pj4gICAgICAgICAgICBzdHJ1Y3QgYW1kZ3B1X2Zwcml2ICpmcHJpdiA9IHAtPmZpbHAtPmRy aXZlcl9wcml2Owo+ID4+Pj4+Pj4gICAgICAgICAgICBzdHJ1Y3QgYW1kZ3B1X2JvX2xpc3RfZW50 cnkgKmU7Cj4gPj4+Pj4+PiArICAgICAgIGJvb2wgbm9faW1wbGljaXRfc3luYyA9IFJFQURfT05D RShmcHJpdi0+dm0ubm9faW1wbGljaXRfc3luYyk7Cj4gPj4+Pj4+PiAgICAgICAgICAgIGludCBy Owo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+ICAgICAgICAgICAgbGlzdF9mb3JfZWFjaF9lbnRyeShlLCAm cC0+dmFsaWRhdGVkLCB0di5oZWFkKSB7Cj4gPj4+Pj4+PiBAQCAtNjU2LDcgKzY1OSw3IEBAIHN0 YXRpYyBpbnQgYW1kZ3B1X2NzX3N5bmNfcmluZ3Moc3RydWN0IGFtZGdwdV9jc19wYXJzZXIgKnAp Cj4gPj4+Pj4+PiAgICAgICAgICAgICAgICAgICAgc3RydWN0IGRtYV9yZXN2ICpyZXN2ID0gYm8t PnRiby5iYXNlLnJlc3Y7Cj4gPj4+Pj4+PiAgICAgICAgICAgICAgICAgICAgZW51bSBhbWRncHVf c3luY19tb2RlIHN5bmNfbW9kZTsKPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiAtICAgICAgICAgICAgICAg c3luY19tb2RlID0gYW1kZ3B1X2JvX2V4cGxpY2l0X3N5bmMoYm8pID8KPiA+Pj4+Pj4+ICsgICAg ICAgICAgICAgICBzeW5jX21vZGUgPSBub19pbXBsaWNpdF9zeW5jIHx8IGFtZGdwdV9ib19leHBs aWNpdF9zeW5jKGJvKSA/Cj4gPj4+Pj4+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICBBTURH UFVfU1lOQ19FWFBMSUNJVCA6IEFNREdQVV9TWU5DX05FX09XTkVSOwo+ID4+Pj4+Pj4gICAgICAg ICAgICAgICAgICAgIHIgPSBhbWRncHVfc3luY19yZXN2KHAtPmFkZXYsICZwLT5qb2ItPnN5bmMs IHJlc3YsIHN5bmNfbW9kZSwKPiA+Pj4+Pj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAmZnByaXYtPnZtKTsKPiA+Pj4+Pj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vYW1kL2FtZGdwdS9hbWRncHVfZHJ2LmMgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdw dS9hbWRncHVfZHJ2LmMKPiA+Pj4+Pj4+IGluZGV4IGMwODBiYTE1YWU3Ny4uZjk4MjYyNmI1MzI4 IDEwMDY0NAo+ID4+Pj4+Pj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvYW1kZ3B1 X2Rydi5jCj4gPj4+Pj4+PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdwdS9hbWRncHVf ZHJ2LmMKPiA+Pj4+Pj4+IEBAIC0xNzI0LDYgKzE3MjQsMjYgQEAgaW50IGFtZGdwdV9maWxlX3Rv X2Zwcml2KHN0cnVjdCBmaWxlICpmaWxwLCBzdHJ1Y3QgYW1kZ3B1X2Zwcml2ICoqZnByaXYpCj4g Pj4+Pj4+PiAgICAgICAgICAgIHJldHVybiAwOwo+ID4+Pj4+Pj4gICAgIH0KPiA+Pj4+Pj4+Cj4g Pj4+Pj4+PiAraW50IGFtZGdwdV9zZXRwYXJhbV9pb2N0bChzdHJ1Y3QgZHJtX2RldmljZSAqZGV2 LCB2b2lkICpkYXRhLAo+ID4+Pj4+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3Qg ZHJtX2ZpbGUgKmZpbHApCj4gPj4+Pj4+PiArewo+ID4+Pj4+Pj4gKyAgICAgICBzdHJ1Y3QgZHJt X2FtZGdwdV9zZXRwYXJhbSAqc2V0cGFyYW0gPSBkYXRhOwo+ID4+Pj4+Pj4gKyAgICAgICBzdHJ1 Y3QgYW1kZ3B1X2Zwcml2ICpmcHJpdiA9IGZpbHAtPmRyaXZlcl9wcml2Owo+ID4+Pj4+Pj4gKwo+ ID4+Pj4+Pj4gKyAgICAgICBzd2l0Y2ggKHNldHBhcmFtLT5wYXJhbSkgewo+ID4+Pj4+Pj4gKyAg ICAgICBjYXNlIEFNREdQVV9TRVRQQVJBTV9OT19JTVBMSUNJVF9TWU5DOgo+ID4+Pj4+Pj4gKyAg ICAgICAgICAgICAgIGlmIChzZXRwYXJhbS0+dmFsdWUpCj4gPj4+Pj4+PiArICAgICAgICAgICAg ICAgICAgICAgICBXUklURV9PTkNFKGZwcml2LT52bS5ub19pbXBsaWNpdF9zeW5jLCB0cnVlKTsK PiA+Pj4+Pj4+ICsgICAgICAgICAgICAgICBlbHNlCj4gPj4+Pj4+PiArICAgICAgICAgICAgICAg ICAgICAgICBXUklURV9PTkNFKGZwcml2LT52bS5ub19pbXBsaWNpdF9zeW5jLCBmYWxzZSk7Cj4g Pj4+Pj4+PiArICAgICAgICAgICAgICAgYnJlYWs7Cj4gPj4+Pj4+PiArICAgICAgIGRlZmF1bHQ6 Cj4gPj4+Pj4+PiArICAgICAgICAgICAgICAgcmV0dXJuIC1FSU5WQUw7Cj4gPj4+Pj4+PiArICAg ICAgIH0KPiA+Pj4+Pj4+ICsKPiA+Pj4+Pj4+ICsgICAgICAgcmV0dXJuIDA7Cj4gPj4+Pj4+PiAr fQo+ID4+Pj4+Pj4gKwo+ID4+Pj4+Pj4gICAgIGNvbnN0IHN0cnVjdCBkcm1faW9jdGxfZGVzYyBh bWRncHVfaW9jdGxzX2ttc1tdID0gewo+ID4+Pj4+Pj4gICAgICAgICAgICBEUk1fSU9DVExfREVG X0RSVihBTURHUFVfR0VNX0NSRUFURSwgYW1kZ3B1X2dlbV9jcmVhdGVfaW9jdGwsIERSTV9BVVRI fERSTV9SRU5ERVJfQUxMT1cpLAo+ID4+Pj4+Pj4gICAgICAgICAgICBEUk1fSU9DVExfREVGX0RS VihBTURHUFVfQ1RYLCBhbWRncHVfY3R4X2lvY3RsLCBEUk1fQVVUSHxEUk1fUkVOREVSX0FMTE9X KSwKPiA+Pj4+Pj4+IEBAIC0xNzQyLDYgKzE3NjIsNyBAQCBjb25zdCBzdHJ1Y3QgZHJtX2lvY3Rs X2Rlc2MgYW1kZ3B1X2lvY3Rsc19rbXNbXSA9IHsKPiA+Pj4+Pj4+ICAgICAgICAgICAgRFJNX0lP Q1RMX0RFRl9EUlYoQU1ER1BVX0dFTV9WQSwgYW1kZ3B1X2dlbV92YV9pb2N0bCwgRFJNX0FVVEh8 RFJNX1JFTkRFUl9BTExPVyksCj4gPj4+Pj4+PiAgICAgICAgICAgIERSTV9JT0NUTF9ERUZfRFJW KEFNREdQVV9HRU1fT1AsIGFtZGdwdV9nZW1fb3BfaW9jdGwsIERSTV9BVVRIfERSTV9SRU5ERVJf QUxMT1cpLAo+ID4+Pj4+Pj4gICAgICAgICAgICBEUk1fSU9DVExfREVGX0RSVihBTURHUFVfR0VN X1VTRVJQVFIsIGFtZGdwdV9nZW1fdXNlcnB0cl9pb2N0bCwgRFJNX0FVVEh8RFJNX1JFTkRFUl9B TExPVyksCj4gPj4+Pj4+PiArICAgICAgIERSTV9JT0NUTF9ERUZfRFJWKEFNREdQVV9TRVRQQVJB TSwgYW1kZ3B1X3NldHBhcmFtX2lvY3RsLCBEUk1fQVVUSHxEUk1fUkVOREVSX0FMTE9XKSwKPiA+ Pj4+Pj4+ICAgICB9Owo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+ICAgICBzdGF0aWMgY29uc3Qgc3RydWN0 IGRybV9kcml2ZXIgYW1kZ3B1X2ttc19kcml2ZXIgPSB7Cj4gPj4+Pj4+PiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvYW1kZ3B1X3ZtLmggYi9kcml2ZXJzL2dwdS9kcm0v YW1kL2FtZGdwdS9hbWRncHVfdm0uaAo+ID4+Pj4+Pj4gaW5kZXggZGRiODVhODVjYmJhLi4wZThj NDQwYzYzMDMgMTAwNjQ0Cj4gPj4+Pj4+PiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdw dS9hbWRncHVfdm0uaAo+ID4+Pj4+Pj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUv YW1kZ3B1X3ZtLmgKPiA+Pj4+Pj4+IEBAIC0zMjEsNiArMzIxLDEyIEBAIHN0cnVjdCBhbWRncHVf dm0gewo+ID4+Pj4+Pj4gICAgICAgICAgICBib29sICAgICAgICAgICAgICAgICAgICBidWxrX21v dmVhYmxlOwo+ID4+Pj4+Pj4gICAgICAgICAgICAvKiBGbGFnIHRvIGluZGljYXRlIGlmIFZNIGlz IHVzZWQgZm9yIGNvbXB1dGUgKi8KPiA+Pj4+Pj4+ICAgICAgICAgICAgYm9vbCAgICAgICAgICAg ICAgICAgICAgaXNfY29tcHV0ZV9jb250ZXh0Owo+ID4+Pj4+Pj4gKyAgICAgICAvKgo+ID4+Pj4+ Pj4gKyAgICAgICAgKiBGbGFnIHRvIGluZGljYXRlIHdoZXRoZXIgaW1wbGljaXQgc3luYyBzaG91 bGQgYWx3YXlzIGJlIHNraXBwZWQgb24KPiA+Pj4+Pj4+ICsgICAgICAgICogdGhpcyBjb250ZXh0 LiBXZSBkbyBub3QgY2FyZSBhYm91dCByYWNlcyBhdCBhbGwsIHVzZXJzcGFjZSBpcyBhbGxvd2Vk Cj4gPj4+Pj4+PiArICAgICAgICAqIHRvIHNob290IGl0c2VsZiB3aXRoIGltcGxpY2l0IHN5bmMg dG8gaXRzIGZ1bGxlc3QgbGlraW5nLgo+ID4+Pj4+Pj4gKyAgICAgICAgKi8KPiA+Pj4+Pj4+ICsg ICAgICAgYm9vbCBub19pbXBsaWNpdF9zeW5jOwo+ID4+Pj4+Pj4gICAgIH07Cj4gPj4+Pj4+Pgo+ ID4+Pj4+Pj4gICAgIHN0cnVjdCBhbWRncHVfdm1fbWFuYWdlciB7Cj4gPj4+Pj4+PiBkaWZmIC0t Z2l0IGEvaW5jbHVkZS91YXBpL2RybS9hbWRncHVfZHJtLmggYi9pbmNsdWRlL3VhcGkvZHJtL2Ft ZGdwdV9kcm0uaAo+ID4+Pj4+Pj4gaW5kZXggMGNiZDE1NDBhZWFjLi45ZWFlMjQ1YzE0ZDYgMTAw NjQ0Cj4gPj4+Pj4+PiAtLS0gYS9pbmNsdWRlL3VhcGkvZHJtL2FtZGdwdV9kcm0uaAo+ID4+Pj4+ Pj4gKysrIGIvaW5jbHVkZS91YXBpL2RybS9hbWRncHVfZHJtLmgKPiA+Pj4+Pj4+IEBAIC01NCw2 ICs1NCw3IEBAIGV4dGVybiAiQyIgewo+ID4+Pj4+Pj4gICAgICNkZWZpbmUgRFJNX0FNREdQVV9W TSAgICAgICAgICAgICAgICAgIDB4MTMKPiA+Pj4+Pj4+ICAgICAjZGVmaW5lIERSTV9BTURHUFVf RkVOQ0VfVE9fSEFORExFICAgICAweDE0Cj4gPj4+Pj4+PiAgICAgI2RlZmluZSBEUk1fQU1ER1BV X1NDSEVEICAgICAgICAgICAgICAgMHgxNQo+ID4+Pj4+Pj4gKyNkZWZpbmUgRFJNX0FNREdQVV9T RVRQQVJBTSAgICAgICAgICAgIDB4MTYKPiA+Pj4+Pj4+Cj4gPj4+Pj4+PiAgICAgI2RlZmluZSBE Uk1fSU9DVExfQU1ER1BVX0dFTV9DUkVBVEUgICAgRFJNX0lPV1IoRFJNX0NPTU1BTkRfQkFTRSAr IERSTV9BTURHUFVfR0VNX0NSRUFURSwgdW5pb24gZHJtX2FtZGdwdV9nZW1fY3JlYXRlKQo+ID4+ Pj4+Pj4gICAgICNkZWZpbmUgRFJNX0lPQ1RMX0FNREdQVV9HRU1fTU1BUCAgICAgIERSTV9JT1dS KERSTV9DT01NQU5EX0JBU0UgKyBEUk1fQU1ER1BVX0dFTV9NTUFQLCB1bmlvbiBkcm1fYW1kZ3B1 X2dlbV9tbWFwKQo+ID4+Pj4+Pj4gQEAgLTcxLDYgKzcyLDcgQEAgZXh0ZXJuICJDIiB7Cj4gPj4+ Pj4+PiAgICAgI2RlZmluZSBEUk1fSU9DVExfQU1ER1BVX1ZNICAgICAgICAgICAgRFJNX0lPV1Io RFJNX0NPTU1BTkRfQkFTRSArIERSTV9BTURHUFVfVk0sIHVuaW9uIGRybV9hbWRncHVfdm0pCj4g Pj4+Pj4+PiAgICAgI2RlZmluZSBEUk1fSU9DVExfQU1ER1BVX0ZFTkNFX1RPX0hBTkRMRSBEUk1f SU9XUihEUk1fQ09NTUFORF9CQVNFICsgRFJNX0FNREdQVV9GRU5DRV9UT19IQU5ETEUsIHVuaW9u IGRybV9hbWRncHVfZmVuY2VfdG9faGFuZGxlKQo+ID4+Pj4+Pj4gICAgICNkZWZpbmUgRFJNX0lP Q1RMX0FNREdQVV9TQ0hFRCAgICAgICAgIERSTV9JT1coRFJNX0NPTU1BTkRfQkFTRSArIERSTV9B TURHUFVfU0NIRUQsIHVuaW9uIGRybV9hbWRncHVfc2NoZWQpCj4gPj4+Pj4+PiArI2RlZmluZSBE Uk1fSU9DVExfQU1ER1BVX1NFVFBBUkFNICAgICAgRFJNX0lPVyhEUk1fQ09NTUFORF9CQVNFICsg RFJNX0FNREdQVV9TRVRQQVJBTSwgc3RydWN0IGRybV9hbWRncHVfc2V0cGFyYW0pCj4gPj4+Pj4+ Pgo+ID4+Pj4+Pj4gICAgIC8qKgo+ID4+Pj4+Pj4gICAgICAqIERPQzogbWVtb3J5IGRvbWFpbnMK PiA+Pj4+Pj4+IEBAIC0zMDYsNiArMzA4LDE0IEBAIHVuaW9uIGRybV9hbWRncHVfc2NoZWQgewo+ ID4+Pj4+Pj4gICAgICAgICAgICBzdHJ1Y3QgZHJtX2FtZGdwdV9zY2hlZF9pbiBpbjsKPiA+Pj4+ Pj4+ICAgICB9Owo+ID4+Pj4+Pj4KPiA+Pj4+Pj4+ICsjZGVmaW5lIEFNREdQVV9TRVRQQVJBTV9O T19JTVBMSUNJVF9TWU5DICAgICAgIDEKPiA+Pj4+Pj4+ICsKPiA+Pj4+Pj4+ICtzdHJ1Y3QgZHJt X2FtZGdwdV9zZXRwYXJhbSB7Cj4gPj4+Pj4+PiArICAgICAgIC8qIEFNREdQVV9TRVRQQVJBTV8q ICovCj4gPj4+Pj4+PiArICAgICAgIF9fdTMyICAgcGFyYW07Cj4gPj4+Pj4+PiArICAgICAgIF9f dTMyICAgdmFsdWU7Cj4gPj4+Pj4+PiArfTsKPiA+Pj4+Pj4+ICsKPiA+Pj4+Pj4+ICAgICAvKgo+ ID4+Pj4+Pj4gICAgICAqIFRoaXMgaXMgbm90IGEgcmVsaWFibGUgQVBJIGFuZCB5b3Ugc2hvdWxk IGV4cGVjdCBpdCB0byBmYWlsIGZvciBhbnkKPiA+Pj4+Pj4+ICAgICAgKiBudW1iZXIgb2YgcmVh c29ucyBhbmQgaGF2ZSBmYWxsYmFjayBwYXRoIHRoYXQgZG8gbm90IHVzZSB1c2VycHRyIHRvCj4g Pj4+Pj4+PiAtLQo+ID4+Pj4+Pj4gMi4zMi4wLnJjMgo+ID4+Pj4+Pj4KPiA+Cj4KCgotLSAKRGFu aWVsIFZldHRlcgpTb2Z0d2FyZSBFbmdpbmVlciwgSW50ZWwgQ29ycG9yYXRpb24KaHR0cDovL2Js b2cuZmZ3bGwuY2gKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 Cg==