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Wed, 22 Jul 2020 07:39:33 -0400 Received: from mail-oi1-x243.google.com (mail-oi1-x243.google.com [IPv6:2607:f8b0:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24E1FC0619DE for ; Wed, 22 Jul 2020 04:39:33 -0700 (PDT) Received: by mail-oi1-x243.google.com with SMTP id r8so1584958oij.5 for ; Wed, 22 Jul 2020 04:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=g9TiRZLPSKHMr8Ff++37IewQa29JTl7u2x6QvpJDSzY=; b=Y7hXQUhJdiARkKQNxqTHTZ+wAkAyDx9PL1FW8VwRs0O4aHcHffMqUchTVQfjgTJXb5 JZNpDjP3MlIHmY8EaB6B2OPT61NK4d1aJj69PrXp/keN7eQ4mdBPRDCWlRwCctpRtcon pB6fyBnJveDM/iUy5w8/CXhV8E3ydB6J3h0d0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=g9TiRZLPSKHMr8Ff++37IewQa29JTl7u2x6QvpJDSzY=; b=TIVL0WchhA+hnEnL+VvwBUVUn8DZlGH2EmtkHBUjB3BMhdVmB2d1aeDw/moRLB1C/U b3DfsOKrAldA24m5i279PgAgWFmwvHHamRgmXoQBIPL7dPeYAdjQC5waqzfrLpsfGYjN eCgT6cDSl7C4Q4HityLxQzhQrPRGZS3PGZYY8eYB4hwN/WDzq0V+f1WiI/0CIWwdWDC5 yDG/B1cpBmk/rrro5rUE55jtw8Q0p6rG9QrlmK5A0q8IuvKNfLTva9WcrTj3F0x+Xpjg G9MVjV5hErci4TtAnJ4aA1QnPlzowJBFZsMf15WGXXQPV9SjB0VRyoRYSTP52QlACaw/ WQlQ== X-Gm-Message-State: AOAM533xnAMBUrU/BFb14J+8KNHTWHycYbQfYDl4Mx/mCJvmeNCjxJAD znMlkvki2ixCS2LKNi5ahWzXlf031miWg/4Aoe66IA== X-Google-Smtp-Source: ABdhPJzY6PHdL/L/QgEPLmGA+g6qf3lZeTpfg/RFXs/QangcGvPjy4yTJwwEFD9BwKm/swCp49wY5XPczQ7jnPAYjJY= X-Received: by 2002:aca:da03:: with SMTP id r3mr6821055oig.14.1595417972307; Wed, 22 Jul 2020 04:39:32 -0700 (PDT) MIME-Version: 1.0 References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> <20200709123339.547390-1-daniel.vetter@ffwll.ch> <93b673b7-bb48-96eb-dc2c-bd4f9304000e@shipmail.org> <20200721074157.GB3278063@phenom.ffwll.local> <3603bb71-318b-eb53-0532-9daab62dce86@amd.com> <57a5eb9d-b74f-8ce4-7199-94e911d9b68b@shipmail.org> <805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> In-Reply-To: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> From: Daniel Vetter Date: Wed, 22 Jul 2020 13:39:21 +0200 Message-ID: Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea To: =?UTF-8?Q?Thomas_Hellstr=C3=B6m_=28Intel=29?= Cc: Dave Airlie , =?UTF-8?Q?Christian_K=C3=B6nig?= , Daniel Stone , linux-rdma , Intel Graphics Development , Maarten Lankhorst , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jason Ekstrand , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Mika Kuoppala , Felix Kuehling , Linux Media Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On Wed, Jul 22, 2020 at 12:31 PM Thomas Hellstr=C3=B6m (Intel) wrote: > > > On 2020-07-22 11:45, Daniel Vetter wrote: > > On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellstr=C3=B6m (Intel) > > wrote: > >> > >> On 2020-07-22 09:11, Daniel Vetter wrote: > >>> On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellstr=C3=B6m (Intel) > >>> wrote: > >>>> On 2020-07-22 00:45, Dave Airlie wrote: > >>>>> On Tue, 21 Jul 2020 at 18:47, Thomas Hellstr=C3=B6m (Intel) > >>>>> wrote: > >>>>>> On 7/21/20 9:45 AM, Christian K=C3=B6nig wrote: > >>>>>>> Am 21.07.20 um 09:41 schrieb Daniel Vetter: > >>>>>>>> On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellstr=C3=B6m = (Intel) > >>>>>>>> wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> On 7/9/20 2:33 PM, Daniel Vetter wrote: > >>>>>>>>>> Comes up every few years, gets somewhat tedious to discuss, le= t's > >>>>>>>>>> write this down once and for all. > >>>>>>>>>> > >>>>>>>>>> What I'm not sure about is whether the text should be more exp= licit in > >>>>>>>>>> flat out mandating the amdkfd eviction fences for long running= compute > >>>>>>>>>> workloads or workloads where userspace fencing is allowed. > >>>>>>>>> Although (in my humble opinion) it might be possible to complet= ely > >>>>>>>>> untangle > >>>>>>>>> kernel-introduced fences for resource management and dma-fences= used > >>>>>>>>> for > >>>>>>>>> completion- and dependency tracking and lift a lot of restricti= ons > >>>>>>>>> for the > >>>>>>>>> dma-fences, including prohibiting infinite ones, I think this m= akes > >>>>>>>>> sense > >>>>>>>>> describing the current state. > >>>>>>>> Yeah I think a future patch needs to type up how we want to make= that > >>>>>>>> happen (for some cross driver consistency) and what needs to be > >>>>>>>> considered. Some of the necessary parts are already there (with = like the > >>>>>>>> preemption fences amdkfd has as an example), but I think some cl= ear docs > >>>>>>>> on what's required from both hw, drivers and userspace would be = really > >>>>>>>> good. > >>>>>>> I'm currently writing that up, but probably still need a few days= for > >>>>>>> this. > >>>>>> Great! I put down some (very) initial thoughts a couple of weeks a= go > >>>>>> building on eviction fences for various hardware complexity levels= here: > >>>>>> > >>>>>> https://gitlab.freedesktop.org/thomash/docs/-/blob/master/Untangli= ng%20dma-fence%20and%20memory%20allocation.odt > >>>>> We are seeing HW that has recoverable GPU page faults but only for > >>>>> compute tasks, and scheduler without semaphores hw for graphics. > >>>>> > >>>>> So a single driver may have to expose both models to userspace and > >>>>> also introduces the problem of how to interoperate between the two > >>>>> models on one card. > >>>>> > >>>>> Dave. > >>>> Hmm, yes to begin with it's important to note that this is not a > >>>> replacement for new programming models or APIs, This is something th= at > >>>> takes place internally in drivers to mitigate many of the restrictio= ns > >>>> that are currently imposed on dma-fence and documented in this and > >>>> previous series. It's basically the driver-private narrow completion= s > >>>> Jason suggested in the lockdep patches discussions implemented the s= ame > >>>> way as eviction-fences. > >>>> > >>>> The memory fence API would be local to helpers and middle-layers lik= e > >>>> TTM, and the corresponding drivers. The only cross-driver-like > >>>> visibility would be that the dma-buf move_notify() callback would no= t be > >>>> allowed to wait on dma-fences or something that depends on a dma-fen= ce. > >>> Because we can't preempt (on some engines at least) we already have > >>> the requirement that cross driver buffer management can get stuck on = a > >>> dma-fence. Not even taking into account the horrors we do with > >>> userptr, which are cross driver no matter what. Limiting move_notify > >>> to memory fences only doesn't work, since the pte clearing might need > >>> to wait for a dma_fence first. Hence this becomes a full end-of-batch > >>> fence, not just a limited kernel-internal memory fence. > >> For non-preemptible hardware the memory fence typically *is* the > >> end-of-batch fence. (Unless, as documented, there is a scheduler > >> consuming sync-file dependencies in which case the memory fence wait > >> needs to be able to break out of that). The key thing is not that we c= an > >> break out of execution, but that we can break out of dependencies, sin= ce > >> when we're executing all dependecies (modulo semaphores) are already > >> fulfilled. That's what's eliminating the deadlocks. > >> > >>> That's kinda why I think only reasonable option is to toss in the > >>> towel and declare dma-fence to be the memory fence (and suck up all > >>> the consequences of that decision as uapi, which is kinda where we > >>> are), and construct something new&entirely free-wheeling for userspac= e > >>> fencing. But only for engines that allow enough preempt/gpu page > >>> faulting to make that possible. Free wheeling userspace fences/gpu > >>> semaphores or whatever you want to call them (on windows I think it's > >>> monitored fence) only work if you can preempt to decouple the memory > >>> fences from your gpu command execution. > >>> > >>> There's the in-between step of just decoupling the batchbuffer > >>> submission prep for hw without any preempt (but a scheduler), but tha= t > >>> seems kinda pointless. Modern execbuf should be O(1) fastpath, with > >>> all the allocation/mapping work pulled out ahead. vk exposes that > >>> model directly to clients, GL drivers could use it internally too, so > >>> I see zero value in spending lots of time engineering very tricky > >>> kernel code just for old userspace. Much more reasonable to do that i= n > >>> userspace, where we have real debuggers and no panics about security > >>> bugs (or well, a lot less, webgl is still a thing, but at least > >>> browsers realized you need to container that completely). > >> Sure, it's definitely a big chunk of work. I think the big win would b= e > >> allowing memory allocation in dma-fence critical sections. But I > >> completely buy the above argument. I just wanted to point out that man= y > >> of the dma-fence restrictions are IMHO fixable, should we need to do > >> that for whatever reason. > > I'm still not sure that's possible, without preemption at least. We > > have 4 edges: > > - Kernel has internal depencies among memory fences. We want that to > > allow (mild) amounts of overcommit, since that simplifies live so > > much. > > - Memory fences can block gpu ctx execution (by nature of the memory > > simply not being there yet due to our overcommit) > > - gpu ctx have (if we allow this) userspace controlled semaphore > > dependencies. Of course userspace is expected to not create deadlocks, > > but that's only assuming the kernel doesn't inject additional > > dependencies. Compute folks really want that. > > - gpu ctx can hold up memory allocations if all we have is > > end-of-batch fences. And end-of-batch fences are all we have without > > preempt, plus if we want backwards compat with the entire current > > winsys/compositor ecosystem we need them, which allows us to inject > > stuff dependent upon them pretty much anywhere. > > > > Fundamentally that's not fixable without throwing one of the edges > > (and the corresponding feature that enables) out, since no entity has > > full visibility into what's going on. E.g. forcing userspace to tell > > the kernel about all semaphores just brings up back to the > > drm_timeline_syncobj design we have merged right now. And that's imo > > no better. > > Indeed, HW waiting for semaphores without being able to preempt that > wait is a no-go. The doc (perhaps naively) assumes nobody is doing that. preempt is a necessary but not sufficient condition, you also must not have end-of-batch memory fences. And i915 has semaphore support and end-of-batch memory fences, e.g. one piece is: commit c4e8ba7390346a77ffe33ec3f210bc62e0b6c8c6 Author: Chris Wilson Date: Tue Apr 7 14:08:11 2020 +0100 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore Sure it preempts, but that's not enough. > > That's kinda why I'm not seeing much benefits in a half-way state: > > Tons of work, and still not what userspace wants. And for the full > > deal that userspace wants we might as well not change anything with > > dma-fences. For that we need a) ctx preempt and b) new entirely > > decoupled fences that never feed back into a memory fences and c) are > > controlled entirely by userspace. And c) is the really important thing > > people want us to provide. > > > > And once we're ok with dma_fence =3D=3D memory fences, then enforcing t= he > > strict and painful memory allocation limitations is actually what we > > want. > > Let's hope you're right. My fear is that that might be pretty painful as > well. Oh it's very painful too: - We need a separate uapi flavour for gpu ctx with preempt instead of end-of-batch dma-fence. - Which needs to be implemented without breaking stuff badly - e.g. we need to make sure we don't probe-wait on fences unnecessarily since that forces random unwanted preempts. - If we want this with winsys integration we need full userspace revisions since all the dma_fence based sync sharing is out (implicit sync on dma-buf, sync_file, drm_syncobj are all defunct since we can only go the other way round). Utter pain, but I think it's better since it can be done driver-by-driver, and even userspace usecase by usecase. Which means we can experiment in areas where the 10+ years of uapi guarantee isn't so painful, learn, until we do the big jump of new zero-interaction-with-memory-management fences become baked in forever into compositor/winsys/modeset protocols. With the other approach of splitting dma-fence we need to do all the splitting first, make sure we get it right, and only then can we enable the use-case for real. That's just not going to happen, at least not in upstream across all drivers. Within a single driver in some vendor tree hacking stuff up is totally fine ofc. -Daniel --=20 Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C82EAC433E6 for ; Wed, 22 Jul 2020 11:39:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C82720729 for ; Wed, 22 Jul 2020 11:39:37 +0000 (UTC) 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dma-buf.rst: Document why indefinite fences are a bad idea To: =?UTF-8?Q?Thomas_Hellstr=C3=B6m_=28Intel=29?= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix Kuehling , Daniel Stone , linux-rdma , Intel Graphics Development , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jason Ekstrand , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Linux Media Mailing List , =?UTF-8?Q?Christian_K=C3=B6nig?= , Mika Kuoppala Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" T24gV2VkLCBKdWwgMjIsIDIwMjAgYXQgMTI6MzEgUE0gVGhvbWFzIEhlbGxzdHLDtm0gKEludGVs KQo8dGhvbWFzX29zQHNoaXBtYWlsLm9yZz4gd3JvdGU6Cj4KPgo+IE9uIDIwMjAtMDctMjIgMTE6 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dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 650BA6E0E6; Wed, 22 Jul 2020 11:39:34 +0000 (UTC) Received: from mail-oi1-x244.google.com (mail-oi1-x244.google.com [IPv6:2607:f8b0:4864:20::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E57C6E10D for ; Wed, 22 Jul 2020 11:39:33 +0000 (UTC) Received: by mail-oi1-x244.google.com with SMTP id r8so1584956oij.5 for ; Wed, 22 Jul 2020 04:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=g9TiRZLPSKHMr8Ff++37IewQa29JTl7u2x6QvpJDSzY=; b=Y7hXQUhJdiARkKQNxqTHTZ+wAkAyDx9PL1FW8VwRs0O4aHcHffMqUchTVQfjgTJXb5 JZNpDjP3MlIHmY8EaB6B2OPT61NK4d1aJj69PrXp/keN7eQ4mdBPRDCWlRwCctpRtcon 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MIME-Version: 1.0 References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> <20200709123339.547390-1-daniel.vetter@ffwll.ch> <93b673b7-bb48-96eb-dc2c-bd4f9304000e@shipmail.org> <20200721074157.GB3278063@phenom.ffwll.local> <3603bb71-318b-eb53-0532-9daab62dce86@amd.com> <57a5eb9d-b74f-8ce4-7199-94e911d9b68b@shipmail.org> <805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> In-Reply-To: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> From: Daniel Vetter Date: Wed, 22 Jul 2020 13:39:21 +0200 Message-ID: To: =?UTF-8?Q?Thomas_Hellstr=C3=B6m_=28Intel=29?= Subject: Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix Kuehling , Daniel Stone , linux-rdma , Intel Graphics Development , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Linux Media Mailing List , =?UTF-8?Q?Christian_K=C3=B6nig?= , Mika Kuoppala Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" T24gV2VkLCBKdWwgMjIsIDIwMjAgYXQgMTI6MzEgUE0gVGhvbWFzIEhlbGxzdHLDtm0gKEludGVs KQo8dGhvbWFzX29zQHNoaXBtYWlsLm9yZz4gd3JvdGU6Cj4KPgo+IE9uIDIwMjAtMDctMjIgMTE6 NDUsIERhbmllbCBWZXR0ZXIgd3JvdGU6Cj4gPiBPbiBXZWQsIEp1bCAyMiwgMjAyMCBhdCAxMDow NSBBTSBUaG9tYXMgSGVsbHN0csO2bSAoSW50ZWwpCj4gPiA8dGhvbWFzX29zQHNoaXBtYWlsLm9y Zz4gd3JvdGU6Cj4gPj4KPiA+PiBPbiAyMDIwLTA3LTIyIDA5OjExLCBEYW5pZWwgVmV0dGVyIHdy b3RlOgo+ID4+PiBPbiBXZWQsIEp1bCAyMiwgMjAyMCBhdCA4OjQ1IEFNIFRob21hcyBIZWxsc3Ry w7ZtIChJbnRlbCkKPiA+Pj4gPHRob21hc19vc0BzaGlwbWFpbC5vcmc+IHdyb3RlOgo+ID4+Pj4g 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[IPv6:2607:f8b0:4864:20::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35F7D6E0E6 for ; Wed, 22 Jul 2020 11:39:33 +0000 (UTC) Received: by mail-oi1-x241.google.com with SMTP id t4so1562742oij.9 for ; Wed, 22 Jul 2020 04:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=g9TiRZLPSKHMr8Ff++37IewQa29JTl7u2x6QvpJDSzY=; b=Y7hXQUhJdiARkKQNxqTHTZ+wAkAyDx9PL1FW8VwRs0O4aHcHffMqUchTVQfjgTJXb5 JZNpDjP3MlIHmY8EaB6B2OPT61NK4d1aJj69PrXp/keN7eQ4mdBPRDCWlRwCctpRtcon pB6fyBnJveDM/iUy5w8/CXhV8E3ydB6J3h0d0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=g9TiRZLPSKHMr8Ff++37IewQa29JTl7u2x6QvpJDSzY=; b=HMnIqNx8ajJTFfycctxoQVmvTdKb8rOWY4MvvxpQ7jYQlKDGL2oNjn/4guhq1H2Z1h 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<805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> In-Reply-To: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> From: Daniel Vetter Date: Wed, 22 Jul 2020 13:39:21 +0200 Message-ID: Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea To: =?UTF-8?Q?Thomas_Hellstr=C3=B6m_=28Intel=29?= X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix Kuehling , Daniel Stone , linux-rdma , Intel Graphics Development , Maarten Lankhorst , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jason Ekstrand , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Linux Media Mailing List , Dave Airlie , =?UTF-8?Q?Christian_K=C3=B6nig?= , Mika Kuoppala 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