From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mirela Simonovic Subject: Re: [PATCH v4 01/10] xen/arm64: Added handling of the trapped access to OSLSR register Date: Wed, 30 May 2018 11:48:04 +0200 Message-ID: References: <20180515114419.7296-1-mirela.simonovic@aggios.com> <20180515114419.7296-2-mirela.simonovic@aggios.com> <4d7e72a3-5b40-f073-4aa4-d8143f1ba71c@arm.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============6190179199786202179==" Return-path: In-Reply-To: <4d7e72a3-5b40-f073-4aa4-d8143f1ba71c@arm.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: Julien Grall Cc: "Edgar E. Iglesias" , Stefano Stabellini , Xen Devel List-Id: xen-devel@lists.xenproject.org --===============6190179199786202179== Content-Type: multipart/alternative; boundary="00000000000058f3b2056d693f32" --00000000000058f3b2056d693f32 Content-Type: text/plain; charset="UTF-8" Hi Julien, Thanks for the feedback. On Tue, May 29, 2018 at 3:19 PM, Julien Grall wrote: > Hi, > > > On 15/05/18 12:44, Mirela Simonovic wrote: > >> Linux/dom0 accesses OSLSR register when saving CPU context during the >> suspend procedure. Xen traps access to this register, but has no handling >> for it. Consequently, Xen injects undef exception to linux, causing it to >> crash. This patch adds handling of the trapped access to OSLSR as ro/raz. >> >> Signed-off-by: Mirela Simonovic >> Reviewed-by: Stefano Stabellini >> Acked-by: Julien Grall >> >> --- >> CC: Stefano Stabellini >> CC: Julien Grall >> --- >> Changes in v2: >> - Commit message fix (arm64 related change instead of arm) >> - Add Stefano's reviewed-by >> >> Changes in v3: >> - Added Julien's acked-by >> --- >> xen/arch/arm/arm64/vsysreg.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c >> index c57ac12503..8f80e1735e 100644 >> --- a/xen/arch/arm/arm64/vsysreg.c >> +++ b/xen/arch/arm/arm64/vsysreg.c >> @@ -57,13 +57,14 @@ void do_sysreg(struct cpu_user_regs *regs, >> * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 >> * >> * Unhandled: >> - * OSLSR_EL1 >> * DBGPRCR_EL1 >> */ >> case HSR_SYSREG_OSLAR_EL1: >> return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); >> case HSR_SYSREG_OSDLR_EL1: >> return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); >> + case HSR_SYSREG_OSLSR_EL1: >> + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); >> > > Looking at this patch again, OSLM (bit[3] and bit[1]) should be 10 as all > other values are reserved. So you want to set bit 3 when the guest read it. > > Could you please let me know is my proposal/understanding correct? Instead of handle_ro_raz, I assume we need this: if ( psr_mode_is_user(regs) ) return inject_undef_exception(regs, hsr); if ( hsr.sysreg.read ) set_user_reg(regs, regidx, 0x8); break; Thanks, Mirela Cheers, > > -- > Julien Grall > --00000000000058f3b2056d693f32 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Julien,

Thanks for the feedback.

On Tue, May 29,= 2018 at 3:19 PM, Julien Grall <julien.grall@arm.com> wro= te:
Hi,


On 15/05/18 12:44, Mirela Simonovic wrote:
Linux/dom0 accesses OSLSR register when saving CPU context during the
suspend procedure. Xen traps access to this register, but has no handling for it. Consequently, Xen injects undef exception to linux, causing it to crash. This patch adds handling of the trapped access to OSLSR as ro/raz.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Acked-by: Julien Grall <julien.grall@arm.com>

---
CC: Stefano Stabellini <sstabellini@kernel.org>
CC: Julien Grall <julien.grall@arm.com>
---
Changes in v2:
- Commit message fix (arm64 related change instead of arm)
- Add Stefano's reviewed-by

Changes in v3:
- Added Julien's acked-by
---
=C2=A0 xen/arch/arm/arm64/vsysreg.c | 3 ++-
=C2=A0 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index c57ac12503..8f80e1735e 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -57,13 +57,14 @@ void do_sysreg(struct cpu_user_regs *regs,
=C2=A0 =C2=A0 =C2=A0 =C2=A0* ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
=C2=A0 =C2=A0 =C2=A0 =C2=A0*
=C2=A0 =C2=A0 =C2=A0 =C2=A0* Unhandled:
-=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 OSLSR_EL1
=C2=A0 =C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 DBGPRCR_EL1
=C2=A0 =C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0 case HSR_SYSREG_OSLAR_EL1:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return handle_wo_wi(regs, regidx, hsr.sy= sreg.read, hsr, 1);
=C2=A0 =C2=A0 =C2=A0 case HSR_SYSREG_OSDLR_EL1:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return handle_raz_wi(regs, regidx, hsr.s= ysreg.read, hsr, 1);
+=C2=A0 =C2=A0 case HSR_SYSREG_OSLSR_EL1:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return handle_ro_raz(regs, regidx, hsr.sysreg.= read, hsr, 1);

Looking at this patch again, OSLM (bit[3] and bit[1]) should be 10 as all o= ther values are reserved. So you want to set bit 3 when the guest read it.<= br>

Could you please let me know is my pro= posal/understanding correct? Instead of=C2=A0hand= le_ro_raz, I assume we need this:

=C2= =A0 =C2=A0 =C2=A0 =C2=A0 if ( psr_mode_is_user(regs) )
=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return inject_undef_exception(regs, hsr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ( hsr.sysreg.read )
=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 set_user_reg(regs, regidx, 0x8);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
=C2=A0
= Thanks,
Mirela

Cheers,

--
Julien Grall

--00000000000058f3b2056d693f32-- --===============6190179199786202179== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0cHM6Ly9saXN0 cy54ZW5wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== --===============6190179199786202179==--