From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A00CDC4332F for ; Sun, 8 Sep 2019 06:32:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6E3A12082C for ; Sun, 8 Sep 2019 06:32:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZK30FGYP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbfIHGch (ORCPT ); Sun, 8 Sep 2019 02:32:37 -0400 Received: from mail-oi1-f195.google.com ([209.85.167.195]:33048 "EHLO mail-oi1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726385AbfIHGch (ORCPT ); Sun, 8 Sep 2019 02:32:37 -0400 Received: by mail-oi1-f195.google.com with SMTP id e12so7938980oie.0 for ; Sat, 07 Sep 2019 23:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=dLtjxvefmPsTqwguHpJKZUk+b0qbK0gCwrT3RQ5TPGM=; b=ZK30FGYPn3DhY9EPZnYFl4udlxLNfjIbrUAKV9kOguKF3EJMxA4yjKnn9rAZQ7Yg1F RnrdtZtuQiORmENPCgWaEnnjDH+i/VGIqpnTDUbvgqTNEab8Yt2KBngTUCWpyAbCt/RY QKZylmaPaTpzmou+Z8AGW3PNvAuUJh9u77aJvrhMxj9lhkdSyhi21km4YX3boFHvOpuc mQTLdaAaPYYLxfMegV3/2nSuo5+sZvO0nayWc43OHOKEPwBU7oky2Udk9yqdQxe7Pq6Z HiEK06nh/NCopBTtkj5dlAWnF74LOJuw5WsLRE+f8NOIogP8wtTJ+yDtxEPPuNcUX0VJ 6+NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dLtjxvefmPsTqwguHpJKZUk+b0qbK0gCwrT3RQ5TPGM=; b=PoaEz1wNqRKkKwHENtEbvO3zh37eqqFO5tSNudqnZXXUpQdtbXdK32QRO1fh19c+lR F+V90ccj/DXHJ5sbpnxHQ3CZBLMezGeQm5mVHBxcFsHbAgFfNtvAfiRguEeLCOegcdww 12oz1eOF6fwbcSpXho1l+HmzIHuwTI2algu8lkHqAvjXBoBQAmy13s/QjxZ1wt/N6AXo R3Rn8+dQj6q0nCwO852GYsv/j4oYMywI8VIFvnqRCV+Nep5Bd4IXyVXZeb5dQchqObp3 Wr4qg63Wg1xFzV3gi+tHcKHRbSIg821XDrDVyDVwT+MY9T8lXZ/JhizWQpN6/mHxTdrb Eoog== X-Gm-Message-State: APjAAAVt+Ctan7AGlN7tSRF559QClYK4DIV+pT2xV6NIesHLClumWybx FHaIuqvpO7/OzTjXVqg+YmCgtvXyeCy7U2zY7g8= X-Google-Smtp-Source: APXvYqz2lgth8Eoypm7N796eC0TY7gK5P0AlQD5/piLA1dX+q7sQ8Yzn3oSizx8asZXvVp7w916dY5CIFMCe2DupVP4= X-Received: by 2002:aca:fdc9:: with SMTP id b192mr12478978oii.50.1567924356321; Sat, 07 Sep 2019 23:32:36 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:2286:0:0:0:0:0 with HTTP; Sat, 7 Sep 2019 23:32:35 -0700 (PDT) In-Reply-To: <20190906215423.23589-1-chunkeey@gmail.com> References: <20190906215423.23589-1-chunkeey@gmail.com> From: Tom Psyborg Date: Sun, 8 Sep 2019 08:32:35 +0200 Message-ID: Subject: Re: [PATCH] ath10k: restore QCA9880-AR1A (v1) detection To: Christian Lamparter Cc: linux-wireless@vger.kernel.org, ath10k@lists.infradead.org, Kalle Valo Content-Type: text/plain; charset="UTF-8" Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org On 06/09/2019, Christian Lamparter wrote: > This patch restores the old behavior that read > the chip_id on the QCA988x before resetting the > chip. This needs to be done in this order since > the unsupported QCA988x AR1A chips fall off the > bus when resetted. Otherwise the next MMIO Op > after the reset causes a BUS ERROR and panic. > > Cc: stable@vger.kernel.org > Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe") > Signed-off-by: Christian Lamparter > --- > drivers/net/wireless/ath/ath10k/pci.c | 36 +++++++++++++++++++-------- > 1 file changed, 25 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/wireless/ath/ath10k/pci.c > b/drivers/net/wireless/ath/ath10k/pci.c > index a0b4d265c6eb..347bb92e4130 100644 > --- a/drivers/net/wireless/ath/ath10k/pci.c > +++ b/drivers/net/wireless/ath/ath10k/pci.c > @@ -3490,7 +3490,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > struct ath10k_pci *ar_pci; > enum ath10k_hw_rev hw_rev; > struct ath10k_bus_params bus_params = {}; > - bool pci_ps; > + bool pci_ps, is_qca988x = false; > int (*pci_soft_reset)(struct ath10k *ar); > int (*pci_hard_reset)(struct ath10k *ar); > u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); > @@ -3500,6 +3500,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > case QCA988X_2_0_DEVICE_ID: > hw_rev = ATH10K_HW_QCA988X; > pci_ps = false; > + is_qca988x = true; > pci_soft_reset = ath10k_pci_warm_reset; > pci_hard_reset = ath10k_pci_qca988x_chip_reset; > targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; > @@ -3619,25 +3620,34 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > goto err_deinit_irq; > } > > + bus_params.dev_type = ATH10K_DEV_TYPE_LL; > + bus_params.link_can_suspend = true; > + /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that > + * fall off the bus during chip_reset. These chips have the same pci > + * device id as the QCA9880 BR4A or 2R4E. So that's why the check. > + */ > + if (is_qca988x) { > + bus_params.chip_id = > + ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); > + if (bus_params.chip_id != 0xffffffff) { > + if (!ath10k_pci_chip_is_supported(pdev->device, > + bus_params.chip_id)) > + goto err_unsupported; > + } > + } > + > ret = ath10k_pci_chip_reset(ar); > if (ret) { > ath10k_err(ar, "failed to reset chip: %d\n", ret); > goto err_free_irq; > } > > - bus_params.dev_type = ATH10K_DEV_TYPE_LL; > - bus_params.link_can_suspend = true; > bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); > - if (bus_params.chip_id == 0xffffffff) { > - ath10k_err(ar, "failed to get chip id\n"); > - goto err_free_irq; > - } > + if (bus_params.chip_id == 0xffffffff) > + goto err_unsupported; > > - if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { > - ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", > - pdev->device, bus_params.chip_id); > + if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) > goto err_free_irq; > - } > > ret = ath10k_core_register(ar, &bus_params); > if (ret) { > @@ -3647,6 +3657,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > > return 0; > > +err_unsupported: > + ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", > + pdev->device, bus_params.chip_id); > + > err_free_irq: > ath10k_pci_free_irq(ar); > ath10k_pci_rx_retry_sync(ar); > -- > 2.23.0 > > Looks fine. For the time being. Have you looked any further to actually support this chip? It seems warm reset is causing bus errors, and cold reset goes through without crash. Firmware gets loaded but is stuck at receiving control response, most likely because of htc packet length or response message length. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1i6qkY-0004rE-74 for ath10k@lists.infradead.org; Sun, 08 Sep 2019 06:32:39 +0000 Received: by mail-oi1-x243.google.com with SMTP id g128so8228306oib.1 for ; Sat, 07 Sep 2019 23:32:36 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20190906215423.23589-1-chunkeey@gmail.com> References: <20190906215423.23589-1-chunkeey@gmail.com> From: Tom Psyborg Date: Sun, 8 Sep 2019 08:32:35 +0200 Message-ID: Subject: Re: [PATCH] ath10k: restore QCA9880-AR1A (v1) detection List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "ath10k" Errors-To: ath10k-bounces+kvalo=adurom.com@lists.infradead.org To: Christian Lamparter Cc: linux-wireless@vger.kernel.org, Kalle Valo , ath10k@lists.infradead.org On 06/09/2019, Christian Lamparter wrote: > This patch restores the old behavior that read > the chip_id on the QCA988x before resetting the > chip. This needs to be done in this order since > the unsupported QCA988x AR1A chips fall off the > bus when resetted. Otherwise the next MMIO Op > after the reset causes a BUS ERROR and panic. > > Cc: stable@vger.kernel.org > Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe") > Signed-off-by: Christian Lamparter > --- > drivers/net/wireless/ath/ath10k/pci.c | 36 +++++++++++++++++++-------- > 1 file changed, 25 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/wireless/ath/ath10k/pci.c > b/drivers/net/wireless/ath/ath10k/pci.c > index a0b4d265c6eb..347bb92e4130 100644 > --- a/drivers/net/wireless/ath/ath10k/pci.c > +++ b/drivers/net/wireless/ath/ath10k/pci.c > @@ -3490,7 +3490,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > struct ath10k_pci *ar_pci; > enum ath10k_hw_rev hw_rev; > struct ath10k_bus_params bus_params = {}; > - bool pci_ps; > + bool pci_ps, is_qca988x = false; > int (*pci_soft_reset)(struct ath10k *ar); > int (*pci_hard_reset)(struct ath10k *ar); > u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); > @@ -3500,6 +3500,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > case QCA988X_2_0_DEVICE_ID: > hw_rev = ATH10K_HW_QCA988X; > pci_ps = false; > + is_qca988x = true; > pci_soft_reset = ath10k_pci_warm_reset; > pci_hard_reset = ath10k_pci_qca988x_chip_reset; > targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; > @@ -3619,25 +3620,34 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > goto err_deinit_irq; > } > > + bus_params.dev_type = ATH10K_DEV_TYPE_LL; > + bus_params.link_can_suspend = true; > + /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that > + * fall off the bus during chip_reset. These chips have the same pci > + * device id as the QCA9880 BR4A or 2R4E. So that's why the check. > + */ > + if (is_qca988x) { > + bus_params.chip_id = > + ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); > + if (bus_params.chip_id != 0xffffffff) { > + if (!ath10k_pci_chip_is_supported(pdev->device, > + bus_params.chip_id)) > + goto err_unsupported; > + } > + } > + > ret = ath10k_pci_chip_reset(ar); > if (ret) { > ath10k_err(ar, "failed to reset chip: %d\n", ret); > goto err_free_irq; > } > > - bus_params.dev_type = ATH10K_DEV_TYPE_LL; > - bus_params.link_can_suspend = true; > bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); > - if (bus_params.chip_id == 0xffffffff) { > - ath10k_err(ar, "failed to get chip id\n"); > - goto err_free_irq; > - } > + if (bus_params.chip_id == 0xffffffff) > + goto err_unsupported; > > - if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { > - ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", > - pdev->device, bus_params.chip_id); > + if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) > goto err_free_irq; > - } > > ret = ath10k_core_register(ar, &bus_params); > if (ret) { > @@ -3647,6 +3657,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev, > > return 0; > > +err_unsupported: > + ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", > + pdev->device, bus_params.chip_id); > + > err_free_irq: > ath10k_pci_free_irq(ar); > ath10k_pci_rx_retry_sync(ar); > -- > 2.23.0 > > Looks fine. For the time being. Have you looked any further to actually support this chip? It seems warm reset is causing bus errors, and cold reset goes through without crash. Firmware gets loaded but is stuck at receiving control response, most likely because of htc packet length or response message length. _______________________________________________ ath10k mailing list ath10k@lists.infradead.org http://lists.infradead.org/mailman/listinfo/ath10k